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Type-assert vconverts to circumvent inferrence restriction on recur…
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…sion
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GianlucaFuwa committed Apr 14, 2024
1 parent 1f886a1 commit 08a505d
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions src/llvm_intrin/conversion.jl
Original file line number Diff line number Diff line change
Expand Up @@ -69,13 +69,13 @@ if (Sys.ARCH === :x86_64) || (Sys.ARCH === :i686)
@inline function vconvert(
::Type{Vec{W,F}},
v::Vec{W,T}
) where {W,F<:FloatingTypes,T<:IntegerTypesHW}
)::Vec{W,F} where {W,F<:FloatingTypes,T<:IntegerTypesHW}
_vconvert(Vec{W,F}, v, True())
end
@inline function vconvert(
::Type{Vec{W,F}},
v::Vec{W,T}
) where {W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
)::Vec{W,F} where {W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
_vconvert(
Vec{W,F},
v,
Expand All @@ -85,7 +85,7 @@ if (Sys.ARCH === :x86_64) || (Sys.ARCH === :i686)
@inline function vconvert(
::Type{F},
v::VecUnroll{N,W,T,Vec{W,T}}
) where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
)::VecUnroll{N,W,F,Vec{W,F}} where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
_vconvert(
Vec{W,F},
v,
Expand All @@ -95,7 +95,7 @@ if (Sys.ARCH === :x86_64) || (Sys.ARCH === :i686)
@inline function vconvert(
::Type{Vec{W,F}},
v::VecUnroll{N,W,T,Vec{W,T}}
) where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
)::VecUnroll{N,W,F,Vec{W,F}} where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
_vconvert(
Vec{W,F},
v,
Expand All @@ -105,7 +105,7 @@ if (Sys.ARCH === :x86_64) || (Sys.ARCH === :i686)
@inline function vconvert(
::Type{VecUnroll{N,W,F,Vec{W,F}}},
v::VecUnroll{N,W,T,Vec{W,T}}
) where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
)::VecUnroll{N,W,F,Vec{W,F}} where {N,W,F<:FloatingTypes,T<:Union{UInt64,Int64}}
_vconvert(
Vec{W,F},
v,
Expand All @@ -116,7 +116,7 @@ else
@generated function vconvert(
::Type{Vec{W,F}},
v::Vec{W,T}
) where {W,F<:FloatingTypes,T<:IntegerTypesHW}
)::Vec{W,F} where {W,F<:FloatingTypes,T<:IntegerTypesHW}
convert_func(T <: Signed ? "sitofp" : "uitofp", F, W, T)
end
end
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