Dev Board Setup
WORK IN PROGRESS
The recommended way of getting started is to
- begin with the Verilog or VHDL 'blink an LED' example that comes with your development board.
- You likely will not need to instantiate a PLL and can use a clock source provided by your board.
- Once that entire flow is confirmed working and you have your LED blinking in hardware, swap out the hand written HDL for PipelineC generated code.
- PipelineC generates a single top level module. Try
pipelinec examples/blink.cusing blink.c. - The top level module name
--topis set totopby default.
- PipelineC generates a single top level module. Try
The below sections detail getting started on a few common development platforms:
TODO ARTY AND PICO-ICE maybe add a altera board some day...
REFRESH AND LINK TO https://github.com/JulianKemmerer/PipelineC/wiki/Example:-Blink-LEDs https://github.com/JulianKemmerer/PipelineC/wiki/Example:-UART-Loopback https://github.com/JulianKemmerer/PipelineC/wiki/Example:-VGA-Graphics (JUST TEST PATTERN) mmaaaaaybe ethernet (pmod on pico-ice)
MAKE NEW page for stream.h and handshake.h docs? copy discord convo
build flow pinout clock name/ports, pll config TODO tristate section
eventually remove/rename OLD https://github.com/JulianKemmerer/PipelineC/wiki/Arty-Board-Examples not needed since list in all examples page anyway...
"just bought my first FPGA development board"
tool version modern not old part need pinout want schematic want blink example or some design that can be loaded to the board and see it works 'from the factory' likely going to run on linux
https://github.com/JulianKemmerer/PipelineC/wiki/Running-the-Tool Vivado and OSS CAD SUITE
constraints and pin io example makefiles / project files pico ice sdk and maybe digilent vivado files walk through vivado new project?
Get blinky working from verilog vhdl equivalent of seeing ASM and knowing how to work the microcontroller specific compiler proves flow, cables, power, programming etc work mention where pin io and off chip clock constraints used
mention icepll and vivado clock wizard
https://github.com/JulianKemmerer/PipelineC/wiki/Running-the-Tool
- reset?
- clocks, const name pll clock, add section to https://github.com/JulianKemmerer/PipelineC/wiki/Modules,-Hierarchy,-Composability and link to
And point to blinky example page show with and without reg as output
and point to UART rx tx and VGA timing examples Sections for each or just one with links to other pages?
Simple math TODO make intro to pipelines pages most of time is global valid ready then global with valid aif need more flexibiity after beginner can start using pipelines with les hepler macros more flexible
Show running xsim (with command line for modelsim too) or looking at ghdl gtkwave output blinky example easy
yosys and nextpnr vivado how to compare resources and timing, where and how to read logs resource types like asm insts, hardware specific advanced
--no synth could be default --comb no args default meet timing, runs synth to check will read timing report and report pass fail
arty and pico-ice specifics how to produce bitstream USB and or JTAG vivado and or dfuutil