During the Advanced Physical Design workshop using OpenLANE and SKY130, I learned about the entire Physical Design process. This training focused on an RTL2GDSII flow using the open-source flow OpenLANE, with the PICORV32A RISC-V core design as an example. I learned about chip floorplanning, library cell design and characterization, pre-layout timing analysis, and the final steps of the RTL2GDSII flow.This repository contains all of the information and resources I have acquired during the workshop.
- Tools Used
- 1 – Inception of open-source EDA, OpenLANE and Sky130 PDK
- How to talk to computers
- IC Terminologies
- Introduction to RISC-V
- Software applications to hardware
- SoC design and OpenLANE
- Simplified RTL to GDSII Flow
- About Openlane flow
- Get familiar to open-source EDA tools
- How to talk to computers
- 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells
- Chip Floor planning considerations
- Library Binding and Placement
- Cell design and characterization flows
- General timing characterization parameters
- 3 - Design and characterize one library cell using Magic Layout tool and ngspice
- Labs for CMOS inverter ngspice simulations
- Inception of Layout – CMOS fabrication process
- Sky130 Tech File Labs
- 4 - Pre-layout timing analysis and importance of good clock tree
- Timing modelling using delay tables
- Timing analysis with ideal clocks using openSTA
- Clock tree synthesis TritonCTS and signal integrity
- Timing analysis with real clocks using openSTA
- 5 - Final steps for RTL2GDS
- Routing and design rule check (DRC)
- PNR interactive flow tutorial
- Acknowledgement
| Tool | Descriptions |
|---|---|
| Yosys | Synthesis of RTL Design |
| ABC | Mapping of Netlist |
| OpenSTA | Static Timing Analysis |
| Magic VLSI | Layout Tool |
| NGSPICE SPICE | Extraction and Simulation |
| OpenROAD | Floorplanning, Placement, CTS, Optimization, Routing |
| TritonRoute | Detailed Routing |
| SPEF_EXTRACTOR | Generation of SPEF file from DEF file |
In RTL2GDS physical design, there are various terms encountered. A few key terms are:
- Package: a material that houses the semiconductor device and protects it from damage. An example is QFN-48 (Quad Flat No-Leads) with 48 pins.
- Chip: sits in the center of the package and connects to the package pins through wire bonding. It contains components like pad, core, interconnects, etc.
- Pads: connect internal signals from the core of the IC to the external pins of the chip. They are organized as a Pad Frame and include input, output, power supply, and ground pads.
- Die: the block of semiconducting material used to build functional circuits, the entire size of the chip.
- Core: contains all the logic units (gates, muxes, etc.) to execute instructions and produce output. The core can have two types of blocks: Foundry IP blocks (e.g. ADC, DAC, PLL, SRAM) designed by foundries, and Macro blocks (e.g. RISC-V SOC, SPI) pure digital logic blocks.
RISC-V (Reduced Instruction Set Computing) is an open-source Instruction Set Architecture (ISA) for computer processors. RISC-V provides a clean and simple ISA, allowing for efficient implementations of processors, while also providing flexibility for custom extensions. The open-source nature of RISC-V allows for easy collaboration and customization, enabling the development of diverse, specialized processors for a wide range of applications. This has led to a growing number of companies and institutions adopting RISC-V for their processors, contributing to its growing popularity and success.
When we run a program on a computer, it goes through several steps to become executable by the hardware. Firstly, the program written in a high level language (such as C) is compiled into assembly language, which is a representation of the program in a language that is specific to the hardware. The assembly language is then converted into machine language, which consists of binary code that can be executed by the hardware.
The system software, which includes the Operating System (OS), Compiler, and Assembler, plays a crucial role in executing the program. The OS handles low-level functions such as input/output operations and memory management. The compiler compiles the program into assembly language, and the assembler then converts the assembly language into machine language.
Finally, the binary code is executed on the chip layout. The interface between the chip layout and the machine language is achieved through RTL (register transfer level) code. This code provides a description of the digital logic that is used to implement the desired behavior in hardware.
To design a digital ASIC with open source, three open source components are needed:
- RTL Designs (found on github.com, librecores.org, and opencores.org)
- EDA Tools (such as OpenROAD, OpenLANE, and QFlow),
- PDK (Process Design Kit) - The PDK is provided by Google and Skywater, and it is a 130nm Production PDK. The PDK acts as a bridge between the designer and the fab and contains important information such as cell libraries, IO libraries, and design rules (DRC, LVS, etc.).
In the process of digital ASIC design
- Synthesis is the step where the RTL code is transformed into a gate level netlist composed of components from a standard cell library.
- Floor planning and power planning involves allocating the silicon area and creating a robust power distribution network. The power network often employs thicker upper metal layers to reduce resistance and IR drop problems.
- Placement is a two-part process, starting with global placement to find the optimal positions for cells which may not be legal, followed by detailed placement to determine the actual legal positions of cells.
- Clock tree synthesis is the distribution of clocks to all flip flops, often structured as a tree such as an H-tree or X-tree.
- Routing involves connecting cells together using horizontal and vertical wires. The router uses information from the PDK such as thickness, pitch, width, and vias for each metal layer, with Sky130 defining 6 routing layers for both global and detailed routing.
- Before sign-off, verification is crucial and includes physical verification such as DRC and LVS, and timing verification. Design Rule Checking (DRC) ensures the final layout complies with all design rules, Layout versus Schematic (LVS) checks if the final layout matches the gate level netlist from the synthesis phase, and timing verification confirms that timing constraints are met.
OpenLANE is a flow that employs various open-source tools to design digital circuits from RTL to GDSII. It features the striVe family of open everything SoCs (Open PDK, Open EDA, Open RTL) and utilizes tools such as Yosys, OpenROAD, Magic, Netgen, and SPEF_Extraction. The flow has two modes of operation: Autonomous and Interactive, and is specifically optimized for the SKYWater 130nm open PDK.
The flow starts with RTL synthesis, where the RTL code is processed by Yosys and translated into a logic circuit using generic components. The circuit can then be optimized and mapped to a standard cell library using the ABC tool, guided by various ABC scripts that implement different synthesis strategies.
OpenLANE also includes design exploration utilities that allow the designer to test different configurations of the design and generate reports that show the number of layout violations. The flow also includes Static Timing Analysis performed by OpenSTA, as well as optional testing steps such as DFT (Scan Insertion, ATPG, Test Pattern Compaction, Fault Coverage, and Fault Simulation).
The physical implementation phase is handled by the OpenROAD application, which performs PnR (FP+PP, Placement, Optimization, CTS, and Routing). The TritonRoute tool is used for detailed routing, and a Logic Equivalence Check (LEC) is performed to ensure the optimized circuit still has equivalent functionality. The fake antenna insertion step is also included to address antenna rule violations, with the Magic tool being used for antenna checking and NetGen for circuit extraction.
Finally, the sign-off stage includes STA, DRC, and LVS, with interconnect RC extraction and further STA performed by OpenSTA, and DRC and LVS performed by the Magic tool.
- Getting starting with working directory and openlane
cd work/tools/openlane_working_dir/openlane/ - to invoke the tool type
dockerto start the docker containter
- Open the OpenLane in interactive mode
./flow.tcl -interactiveand Set the package required by OpenLanepackage require openlane 0.9
- select the design
cd designs/picorv32a
- Prepare the design
prep -design picorv32a
- checking whether a merged file is created in the folder
- Run the synthesis
run_synthesis
- View the synthesis statistics
- To calculate the flop ratio
flop ration = no of d flip flops/total no of cells = 1613/18036 = 0.089 = 89%
- floorplan in openlane
run_floorplan
The picorv32a.floorplan.def file was generated in the ./results/floorplan directory by this command.
- We use the Magic tool to view the floorplan, and we need three files to do so:
- Magic Tech file : sky130A.tech
- LEF file : merged.lef
- Def file of floorplan : picorv32a.floorplan.def
magic -T <location of techfile> lef read <loction of lef file> def read <location of floorplan def file>
~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/27-01_19-20/results/floorplan$
magic -T /home/venkykamatham1998/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
The above command can be used to view the floorplan in the Magic tool.
- placement in openlane
run_placement
The picorv32a.placement.def file was generated in the ./results/placement directory by this command.
magic -T <location of techfile> lef read <loction of lef file> def read <location of placement def file>
~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/27-01_19-20/results/placement$
magic -T /home/venkykamatham1998/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
The typical standard cell design flow consists of 3 elements :
- Inputs - PDKs , DRC & LVS rules, SPICE models, library & user-defined specs
- Design Steps - Circuit design, layout design, characterization
- Outputs - CDL(circuit description lanuage), GDSII, LEF, extracted spice netlist(.crc)
% set ::env(FP_IO_MODE) 2
2
% run_floorplan
To see how I/O pins are aligned after changing the value in ioPlacer
Spice Simulations (Pre-Layout) The spice simulations mainly consist of :
- Spice deck - component connectivity, component values, identify nodes, name nodes
- NGspice introduction
- Static behaviour evaluation
- At first we need to git clone the standard cells and command is :
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
- After cloning the repo, navigate to the vsdstdcelldesign directory and use magic to view the sky130_inv.mag file.
- Before opening we need magic tech file and copy the tech file in vsdstdcelldesign directority
cp sky130A.tech /home/venkykamatham1998/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign/
- To view the layout use this command
magic -T sky130A.tech sky130_inv.mag &
16 mask CMOS fabrication process
https://www.vlsisystemdesign.com/wp-content/uploads/2017/07/16-mask-process.pdf
- To view the layout press
sfor select,zfor zoom and intkconltype what cammand to see the mask layers
- We should extract the parasitics and characterise the design. We open the tkcon window and execute the following commands:
extract all
ext2spice cthresh 0 rthresh 0
ext2spice
The extracted file
We then modify the spice file so that we can plot a transient response:
* SPICE3 file created from sky130_inv.ext - technology: sky130A
.option scale=0.01u
.include ./libs/pshort.lib
.include ./libs/nshort.lib
* .subckt sky130_inv A Y VPWR VGND
M0 Y A VGND VGND nshort_model.0 ad=1435 pd=152 as=1365 ps=148 w=35 l=23
M1 Y A VPWR VPWR pshort_model.0 ad=1443 pd=152 as=1517 ps=156 w=37 l=23
C0 A VPWR 0.08fF
C1 Y VPWR 0.08fF
C2 A Y 0.02fF
C3 Y VGND 0.18fF
C4 VPWR VGND 0.74fF
* .ends
* Power supply
VDD VPWR 0 3.3V
VSS VGND 0 0V
* Input Signal
Va A VGND PULSE(0V 3.3V 0 0.1ns 0.1ns 2ns 4ns)
* Simulation Control
.tran 1n 20n
.control
run
.endc
.end
- Open the spice file by typing
ngspice sky130A_inv.spice - Generate a graph using
plot y vs time a
- rise transiton - time taken by output waveform to transit from 20%(0.66) to 80%(2.64) of VDD(3.3 max value) = 2.19945 - 2.15722 = 0.03728 ns
- fall transition - time taken by output waveform to transit from 80% (2.64) to 20% (0.66) of VDD = 4.06716 - 4.0394 = 0.02766 ns
- rise cell delay - The difference between the time when output as well as input is at 50% (1.65) i.e falling at 50% of output is rising = 2.18132 - 2.14945 = 0.03187 ns
- fall cell delay - The difference between the time when output as well as input is at 50% (1.65) i.e falling at 50% of input is rising = 4.059292 - 4.04958 = 0.009712 ns
- OpenLANE is a tool for place and route, which places cells in a design. When using this tool, the full information contained in the .mag file, which includes boundry,power and ground, logic, etc., is not necessary. Instead, only the essential information, such as the placement boundary, power and ground rails, and input and output ports, is required. This information is contained in lef files, which protect the IP(intellectual property).
- The goal is to extract the lef file from the .mag file and use it to replace the standard cells in the design. There are guidelines to follow when creating a standard cell set for use in place and route
-
I/p and O/p port must lies on the intersection of the vertical and horizontal tracks
-
Width oof the std cell should be in the odd ultiples of the track pitch
-
Height should be odd multiples of vertical track pitch
-
To run the previous flow follow this command
-
prep -design picorv32a -tag
- In these directory
/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/we can find tracks
~/Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign$ cd ../../pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/
- tpye command
less tracks.info
less tracks.info
- open the layout from vsdstdcelldesign directory
magic -T sky130.tech sky130_inv.mag
In the tkon terminal, use the grid command to compare the tracks' information
The three guidelines are clearly shown in the illustration in this image
- The information from the .mag file will be extracted into a LEF file, which will contain essential details for placement and routing, such as cell dimensions, port information, and specific properties. The first step in creating the LEF file is to clearly define the port definitions, including the class and intended use of each port
- Save the mag file and relaunch the magic tool. Then run the command below to create the lef file
lef write
- The prior command creates a.lef file. Now, use the following command to copy the lef file into the picrorv32a directory.
cp <path to the file> <path to the target location>
- Add the folowing to config.tcl inside the picorv32a
Design
set ::env(DESIGN_NAME) "picorv32a"
set ::env(VERILOG_FILES) "./designs/picorv32a/src/picorv32a.v"
set ::env(SDC_FILE) "./designs/picorv32a/src/picorv32a.sdc"
set ::env(CLOCK_PERIOD) "5.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(LIB_SYNTH) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(LIB_FASTEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__fast.lib"
set ::env(LIB_SLOWEST) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__slow.lib"
set ::env(LIB_TYPICAL) "$::env(OPENLANE_ROOT)/designs/picorv32a/src/sky130_fd_sc_hd__typical.lib"
set ::env(EXTRA_LEFS) [glob $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/src/*.lef]
set ::env(FP_CORE_UTIL) 65
set ::env(FP_IO_VMETAL) 4
set ::env(FP_IO_HMETAL) 3
set filename $::env(OPENLANE_ROOT)/designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
- Connect the newly created lef file to the OpenLANE flow using
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
- run synthesis -
run_synthesis
- Change a few variables to reduce the negative slack. We will now change the variables "on the flight". To see the current value of the variables before changing them, use echo $::env(SYNTH STRATEGY):
% echo $::env(SYNTH_STRATEGY)
AREA 0
% set ::env(SYNTH_STRATEGY) 1
% echo $::env(SYNTH_BUFFERING)
1
% echo $::env(SYNTH_SIZING)
0
% set ::env(SYNTH_SIZING) 1
% echo $::env(SYNTH_DRIVING_CELL)
sky130_fd_sc_hd__inv_8
- run floorplan
since the openlane is new version it doesn't support
run_floorplancommand we need to use alternatives commands as follows
init_floorplan
place_io
global_placement_or
detailed_placement
tap_decap_or
detailed_placement
gen_pdn
run_cts
run_routing
- Open the def file via magic
- Now, using the command, we perform a post-synthesis analysis in OpenSTA
sta pre_sta.conf
- Kunal Ghosh - Co-founder of VSD
- Nickson Jose - Instructor