This repository contains the supplementary materials corresponding to the paper "Time Sharing - A Novel Approach to Low-Latency Masking" accepted for publication in CHES 2024. We include the HDL source code(Verilog), corresponding netlists and formal verification results for the S-Boxes of PRINCE and AES.
Please refer to README files present in the subfolders for more information.
D. Kumar S. V., S. Dhooghe, J. Balasch, B. Gierlichs, I. Verbauwhede "Time Sharing - A Novel Approach to Low-Latency Masking" IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) 2024, Volume 3. to appear