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  • The University of Hong Kong
  • China
  • 14:02 (UTC +08:00)

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  1. MIPS32-pipelined-processor MIPS32-pipelined-processor Public

    a MIPS32 pipelined processor impelmented by Verilog HDL

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  2. FPGA-AES-encryptor FPGA-AES-encryptor Public

    AES processor impelmented by Verilog. This processor can run at the frequency of 100MHz and take 10 cycles to encrypt an 128-bit plain text.The processor uses several simple commands and state bits…

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  5. KevinLikesDringCoffe.github.io KevinLikesDringCoffe.github.io Public

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    Using FPGA parellel computing to accelerate the FEA

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