A MIPS32 pipelined processor impelmented by Verilog HDL
- Program counter
- Instruction ROM
- Instruction decoder
- Harzard resolve unit(partly)
- Execution unit
- Register file
- ori
- and
- or
- xor
- nor
- andi
- xori
- lui
- sll
- srl
- sra
- sllv
- srlv
- srav
- nop
- ssnop
- movn
- movz
- Condition resolve unit
- Branch resolve unit
- jr
- jalr
- j
- jal
- beq
- bgtz
- blez
- bne
- bltz
- bltzal
- bgez
- bgezal
- b instruction can be operated as beq r0,offset
- bal instruction can be operated as bgezal r0,offset
- Data ram
- Memory stage ram interface
- addu
- subu
- lb
- lbu
- lh
- lhu
- lw
- lwl
- lwr
- sb
- sh
- sw
- swl
- swr
A five stage pipeline which contains fetch, decode, execution, memory and writeback stages. The branch delay slot is removed in this implementation. The branch is detected at decode stage. Data hazard is resolve by forwarding register value from EX and MEM stage to the ID stage.