Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Header changes for Intel's Task Sequence extension #323

Draft
wants to merge 10 commits into
base: main
Choose a base branch
from
Draft

Header changes for Intel's Task Sequence extension #323

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
10 commits
Select commit Hold shift + click to select a range
87c1c58
update spirv.bf
tiwaria1 Mar 14, 2023
99ea087
update grammar json file
tiwaria1 Mar 14, 2023
7d7ddbf
update .cs file
tiwaria1 Mar 14, 2023
1d86ac2
update spirv.h
tiwaria1 Mar 14, 2023
d1569cc
update spirv.hpp
tiwaria1 Mar 14, 2023
1eef4a9
update spirv.hpp11
tiwaria1 Mar 14, 2023
0767fc0
update spirv.json
tiwaria1 Mar 14, 2023
76106b5
update spirv.lua
tiwaria1 Mar 14, 2023
bcd0bf2
update spirv.py
tiwaria1 Mar 14, 2023
053202b
update spirv.d
tiwaria1 Mar 14, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.bf
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1157,6 +1157,7 @@ namespace Spv
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
TaskSequenceINTEL = 6162,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1970,6 +1971,10 @@ namespace Spv
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
57 changes: 57 additions & 0 deletions include/spirv/unified1/spirv.core.grammar.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9151,6 +9151,56 @@
"capabilities" : [ "SplitBarrierINTEL" ],
"version" : "None"
},
{
"opname" : "OpTaskSequenceCreateINTEL",
"class" : "Reserved",
"opcode" : 6163,
"operands" : [
{ "kind" : "IdRef", "name" : "'Pointer'" },
{ "kind" : "IdRef", "name" : "'Function Pointer'" },
{ "kind" : "LiteralInteger", "name" : "'Pipelined'" },
{ "kind" : "LiteralInteger", "name" : "'UseStallEnableClusters'" }
],
"capabilities" : [ "TaskSequenceINTEL" ],
"extensions" : [ "SPV_INTEL_task_sequence" ],
"version" : "None"
},
{
"opname" : "OpTaskSequenceAsyncINTEL",
"class" : "Reserved",
"opcode" : 6164,
"operands" : [
{ "kind" : "IdRef", "name" : "'Pointer'" },
{ "kind" : "LiteralInteger", "name" : "'AsyncCapacity'" },
{ "kind" : "LiteralInteger", "quantifier" : "*", "name" : "'Async Function Parameters'" }
],
"capabilities" : [ "TaskSequenceINTEL" ],
"extensions" : [ "SPV_INTEL_task_sequence" ],
"version" : "None"
},
{
"opname" : "OpTaskSequenceGetINTEL",
"class" : "Reserved",
"opcode" : 6165,
"operands" : [
{ "kind" : "IdRef", "name" : "'Pointer'" },
{ "kind" : "LiteralInteger", "name" : "'GetCapacity'" }
],
"capabilities" : [ "TaskSequenceINTEL" ],
"extensions" : [ "SPV_INTEL_task_sequence" ],
"version" : "None"
},
{
"opname" : "OpTaskSequenceReleaseINTEL",
"class" : "Reserved",
"opcode" : 6166,
"operands" : [
{ "kind" : "IdRef", "name" : "'Pointer'" }
],
"capabilities" : [ "TaskSequenceINTEL" ],
"extensions" : [ "SPV_INTEL_task_sequence" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
Expand Down Expand Up @@ -15049,6 +15099,13 @@
"extensions" : [ "SPV_INTEL_kernel_attributes" ],
"version" : "None"
},
{
"enumerant" : "TaskSequenceINTEL",
"value" : 6162,
"capabilities" : [ "FunctionPointersINTEL" ],
"extensions" : [ "SPV_INTEL_task_sequence" ],
"version" : "None"
},
{
"enumerant" : "FPGALatencyControlINTEL",
"value" : 6171,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.cs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1156,6 +1156,7 @@ public enum Capability
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
TaskSequenceINTEL = 6162,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1969,6 +1970,10 @@ public enum Op
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1156,6 +1156,7 @@ typedef enum SpvCapability_ {
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
SpvCapabilityTaskSequenceINTEL = 6162,
SpvCapabilityFPGALatencyControlINTEL = 6171,
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1967,6 +1968,10 @@ typedef enum SpvOp_ {
SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpTaskSequenceCreateINTEL = 6163,
SpvOpTaskSequenceAsyncINTEL = 6164,
SpvOpTaskSequenceGetINTEL = 6165,
SpvOpTaskSequenceReleaseINTEL = 6166,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1152,6 +1152,7 @@ enum Capability {
CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
CapabilityFPGAKernelAttributesv2INTEL = 6161,
CapabilityTaskSequenceINTEL = 6162,
CapabilityFPGALatencyControlINTEL = 6171,
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1963,6 +1964,10 @@ enum Op {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp11
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1152,6 +1152,7 @@ enum class Capability : unsigned {
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
TaskSequenceINTEL = 6162,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1963,6 +1964,10 @@ enum class Op : unsigned {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1132,6 +1132,7 @@
"BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
"FPGAKernelAttributesv2INTEL": 6161,
"TaskSequenceINTEL": 6162,
"FPGALatencyControlINTEL": 6171,
"FPGAArgumentInterfacesINTEL": 6174,
"GroupUniformArithmeticKHR": 6400
Expand Down Expand Up @@ -1953,6 +1954,10 @@
"OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpTaskSequenceCreateINTEL": 6163,
"OpTaskSequenceAsyncINTEL": 6164,
"OpTaskSequenceGetINTEL": 6165,
"OpTaskSequenceReleaseINTEL": 6166,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.lua
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1114,6 +1114,7 @@ spv = {
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
TaskSequenceINTEL = 6162,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1914,6 +1915,10 @@ spv = {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1114,6 +1114,7 @@
'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
'FPGAKernelAttributesv2INTEL' : 6161,
'TaskSequenceINTEL': 6162,
'FPGALatencyControlINTEL' : 6171,
'FPGAArgumentInterfacesINTEL' : 6174,
'GroupUniformArithmeticKHR' : 6400,
Expand Down Expand Up @@ -1914,6 +1915,10 @@
'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpTaskSequenceCreateINTEL': 6163,
'OpTaskSequenceAsyncINTEL': 6164,
'OpTaskSequenceGetINTEL': 6165,
'OpTaskSequenceReleaseINTEL': 6166,
'OpGroupIMulKHR' : 6401,
'OpGroupFMulKHR' : 6402,
'OpGroupBitwiseAndKHR' : 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spv.d
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1159,6 +1159,7 @@ enum Capability : uint
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
FPGAKernelAttributesv2INTEL = 6161,
TaskSequenceINTEL = 6162,
FPGALatencyControlINTEL = 6171,
FPGAArgumentInterfacesINTEL = 6174,
GroupUniformArithmeticKHR = 6400,
Expand Down Expand Up @@ -1972,6 +1973,10 @@ enum Op : uint
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpTaskSequenceCreateINTEL = 6163,
OpTaskSequenceAsyncINTEL = 6164,
OpTaskSequenceGetINTEL = 6165,
OpTaskSequenceReleaseINTEL = 6166,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down