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Add SPV_EXT_arithmetic_fence #450

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merged 3 commits into from
Oct 2, 2024
Merged

Add SPV_EXT_arithmetic_fence #450

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5b54c9c
Add SPV_EXT_arithmetic_fence
MrSidims Sep 24, 2024
ce256a3
Also add INTEL extension for tooling
MrSidims Sep 25, 2024
63994f1
Revert "Also add INTEL extension for tooling"
MrSidims Oct 2, 2024
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2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.bf
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Original file line number Diff line number Diff line change
Expand Up @@ -1261,6 +1261,7 @@ namespace Spv
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2INTEL = 6150,
FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2225,6 +2226,7 @@ namespace Spv
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down
18 changes: 18 additions & 0 deletions include/spirv/unified1/spirv.core.grammar.json
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Expand Up @@ -9920,6 +9920,18 @@
"capabilities" : [ "SplitBarrierINTEL" ],
"version" : "None"
},
{
"opname" : "OpArithmeticFenceEXT",
"class" : "Miscellaneous",
"opcode" : 6145,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "'Target '" }
],
"capabilities" : [ "ArithmeticFenceEXT" ],
"version" : "None"
},
{
"opname" : "OpSubgroupBlockPrefetchINTEL",
"class" : "Group",
Expand Down Expand Up @@ -16741,6 +16753,12 @@
"extensions" : [ "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
"enumerant" : "ArithmeticFenceEXT",
"value" : 6144,
"extensions" : [ "SPV_EXT_arithmetic_fence" ],
"version" : "None"
},
{
"enumerant" : "FPGAClusterAttributesV2INTEL",
"value" : 6150,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.cs
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Expand Up @@ -1260,6 +1260,7 @@ public enum Capability
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2INTEL = 6150,
FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2224,6 +2225,7 @@ public enum Op
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.h
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Expand Up @@ -1231,6 +1231,7 @@ typedef enum SpvCapability_ {
SpvCapabilityDebugInfoModuleINTEL = 6114,
SpvCapabilityBFloat16ConversionINTEL = 6115,
SpvCapabilitySplitBarrierINTEL = 6141,
SpvCapabilityArithmeticFenceEXT = 6144,
SpvCapabilityFPGAClusterAttributesV2INTEL = 6150,
SpvCapabilityFPGAKernelAttributesv2INTEL = 6161,
SpvCapabilityFPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2170,6 +2171,7 @@ typedef enum SpvOp_ {
SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpArithmeticFenceEXT = 6145,
SpvOpSubgroupBlockPrefetchINTEL = 6221,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
Expand Down Expand Up @@ -2916,6 +2918,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3828,6 +3831,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case SpvCapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
case SpvCapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
Expand Down Expand Up @@ -4713,6 +4717,7 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp
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Expand Up @@ -1227,6 +1227,7 @@ enum Capability {
CapabilityDebugInfoModuleINTEL = 6114,
CapabilityBFloat16ConversionINTEL = 6115,
CapabilitySplitBarrierINTEL = 6141,
CapabilityArithmeticFenceEXT = 6144,
CapabilityFPGAClusterAttributesV2INTEL = 6150,
CapabilityFPGAKernelAttributesv2INTEL = 6161,
CapabilityFPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2166,6 +2167,7 @@ enum Op {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down Expand Up @@ -2912,6 +2914,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3824,6 +3827,7 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
Expand Down Expand Up @@ -4709,6 +4713,7 @@ inline const char* OpToString(Op value) {
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case OpGroupIMulKHR: return "OpGroupIMulKHR";
case OpGroupFMulKHR: return "OpGroupFMulKHR";
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp11
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Expand Up @@ -1227,6 +1227,7 @@ enum class Capability : unsigned {
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2INTEL = 6150,
FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2166,6 +2167,7 @@ enum class Op : unsigned {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down Expand Up @@ -2912,6 +2914,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break;
case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3824,6 +3827,7 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL";
case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL";
case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL";
case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT";
case CapabilityFPGAClusterAttributesV2INTEL: return "FPGAClusterAttributesV2INTEL";
case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL";
case CapabilityFPMaxErrorINTEL: return "FPMaxErrorINTEL";
Expand Down Expand Up @@ -4709,6 +4713,7 @@ inline const char* OpToString(Op value) {
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT";
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case OpGroupIMulKHR: return "OpGroupIMulKHR";
case OpGroupFMulKHR: return "OpGroupFMulKHR";
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.json
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Expand Up @@ -1204,6 +1204,7 @@
"DebugInfoModuleINTEL": 6114,
"BFloat16ConversionINTEL": 6115,
"SplitBarrierINTEL": 6141,
"ArithmeticFenceEXT": 6144,
"FPGAClusterAttributesV2INTEL": 6150,
"FPGAKernelAttributesv2INTEL": 6161,
"FPMaxErrorINTEL": 6169,
Expand Down Expand Up @@ -2168,6 +2169,7 @@
"OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpArithmeticFenceEXT": 6145,
"OpSubgroupBlockPrefetchINTEL": 6221,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.lua
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Expand Up @@ -1218,6 +1218,7 @@ spv = {
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2INTEL = 6150,
FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2157,6 +2158,7 @@ spv = {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.py
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Expand Up @@ -1189,6 +1189,7 @@
'DebugInfoModuleINTEL' : 6114,
'BFloat16ConversionINTEL' : 6115,
'SplitBarrierINTEL' : 6141,
'ArithmeticFenceEXT' : 6144,
'FPGAClusterAttributesV2INTEL' : 6150,
'FPGAKernelAttributesv2INTEL' : 6161,
'FPMaxErrorINTEL' : 6169,
Expand Down Expand Up @@ -2107,6 +2108,7 @@
'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpArithmeticFenceEXT' : 6145,
'OpSubgroupBlockPrefetchINTEL' : 6221,
'OpGroupIMulKHR' : 6401,
'OpGroupFMulKHR' : 6402,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spv.d
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Expand Up @@ -1263,6 +1263,7 @@ enum Capability : uint
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2INTEL = 6150,
FPGAKernelAttributesv2INTEL = 6161,
FPMaxErrorINTEL = 6169,
Expand Down Expand Up @@ -2227,6 +2228,7 @@ enum Op : uint
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpArithmeticFenceEXT = 6145,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
Expand Down