Use bitwise and instead of multiple cmp operations

Signed-off-by: Sudarsanam, Arvind <arvind.sudarsanam@intel.com>
KhronosGroup · Sep 12, 2023 · 1db155b · 1db155b
1 parent afe1796
commit 1db155b
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Showing 2 changed files with 13 additions and 11 deletions.
diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
@@ -4451,13 +4451,15 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
       auto *BitCastToInt =
           BM->addUnaryInst(OpBitcast, OpSPIRVTy, InputFloat, BB);
       if (FPClass & fcPosZero && FPClass & fcNegZero) {
-        auto *TestIsPosZero =
-            SetUpCMPToZero(BitCastToInt, true /*'positive' zero*/);
-        auto *TestIsNegZero =
-            SetUpCMPToZero(BitCastToInt, false /*'negated' zero*/);
-        auto *TestIsZero = BM->addInstTemplate(
-            OpLogicalOr, {TestIsPosZero->getId(), TestIsNegZero->getId()}, BB,
-            ResTy);
+        APInt ZeroInt = APInt::getZero(BitSize);
+        auto *ZeroConst =
+            transValue(Constant::getIntegerValue(IntOpLLVMTy, ZeroInt), BB);
+        APInt SignedMaxInt = APInt::getSignedMaxValue(BitSize);
+        auto *SignedMaxConst =
+            transValue(Constant::getIntegerValue(IntOpLLVMTy, SignedMaxInt), BB);
+	auto *BitwiseAndRes =
+	    BM->addBinaryInst(OpBitwiseAnd, OpSPIRVTy, BitCastToInt, SignedMaxConst, BB);
+        auto *TestIsZero = BM->addCmpInst(OpIEqual, ResTy, BitwiseAndRes, ZeroConst, BB);
         ResultVec.emplace_back(GetInvertedTestIfNeeded(TestIsZero));
       } else if (FPClass & fcPosZero) {
         auto *TestIsPosZero =

diff --git a/test/llvm-intrinsics/fpclass.ll b/test/llvm-intrinsics/fpclass.ll
@@ -21,6 +21,7 @@
 ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#QNanBitConst:]] 2143289344
 ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#MantissaConst:]] 8388607
 ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#ZeroConst:]] 0
+; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#MaxConst:]] 2147483647
 ; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#NegatedZeroConst:]] 2147483648
 ; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#QNanBitConst64:]] 0 2146959360
 ; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#MantissaConst64:]] 4294967295 1048575
@@ -308,10 +309,9 @@ define i1 @test_class_zero(float %arg) {
 ; CHECK-SPIRV-EMPTY:
 ; CHECK-SPIRV-NEXT: Label
 ; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
-; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#EqualPos:]] [[#BitCast]] [[#ZeroConst]]
-; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#EqualNeg:]] [[#BitCast]] [[#NegatedZeroConst]]
-; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Result:]] [[#EqualPos]] [[#EqualNeg]]
-; CHECK-SPIRV-NEXT: ReturnValue [[#Result]]
+; CHECK-SPIRV-NEXT: BitwiseAnd [[#Int32Ty]] [[#BitwiseAndRes:]] [[#BitCast]] [[#MaxConst]]
+; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#EqualPos:]] [[#BitwiseAndRes]] [[#ZeroConst]]
+; CHECK-SPIRV-NEXT: ReturnValue [[#EqualPos]]
   %val = call i1 @llvm.is.fpclass.f32(float %arg, i32 96)
   ret i1 %val
 }