Skip to content

Commit

Permalink
Apply suggestions
Browse files Browse the repository at this point in the history
  • Loading branch information
@vmaksimo
vmaksimo committed Nov 17, 2023
1 parent 251a75c commit a0c4f2e
Show file tree
Hide file tree
Showing 4 changed files with 49 additions and 20 deletions.
2 changes: 2 additions & 0 deletions lib/SPIRV/OCLUtil.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,8 @@ typedef SPIRVMap<OCLMemOrderKind, unsigned, MemorySemanticsMask> OCLMemOrderMap;

typedef SPIRVMap<OCLScopeKind, Scope> OCLMemScopeMap;

typedef SPIRVMap<std::string, Scope> OCLStrMemScopeMap;

typedef SPIRVMap<std::string, SPIRVGroupOperationKind>
SPIRSPIRVGroupOperationMap;

Expand Down
11 changes: 10 additions & 1 deletion lib/SPIRV/SPIRVRegularizeLLVM.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -467,7 +467,16 @@ bool SPIRVRegularizeLLVMBase::regularize() {
// comparator, which matches with semantics of the flag returned by
// cmpxchg.
Value *Ptr = Cmpxchg->getPointerOperand();
Value *MemoryScope = getInt32(M, spv::ScopeDevice);
SmallVector<StringRef> SSIDs;
Cmpxchg->getContext().getSyncScopeNames(SSIDs);

spv::Scope S;
// Fill unknown synscope value to default Device scope.
if (!OCLStrMemScopeMap::find(SSIDs[Cmpxchg->getSyncScopeID()].str(),
&S)) {
S = ScopeDevice;
}
Value *MemoryScope = getInt32(M, S);
auto SuccessOrder = static_cast<OCLMemOrderKind>(
llvm::toCABI(Cmpxchg->getSuccessOrdering()));
auto FailureOrder = static_cast<OCLMemOrderKind>(
Expand Down
33 changes: 25 additions & 8 deletions lib/SPIRV/SPIRVWriter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1731,11 +1731,16 @@ SPIRVValue *LLVMToSPIRVBase::transAtomicStore(StoreInst *ST,
SPIRVBasicBlock *BB) {
SmallVector<StringRef> SSIDs;
ST->getContext().getSyncScopeNames(SSIDs);
std::vector<Value *> Ops{
ST->getPointerOperand(),
getUInt32(M, map<Scope>(SSIDs[ST->getSyncScopeID()].str())),
getUInt32(M, transAtomicOrdering(ST->getOrdering())),
ST->getValueOperand()};

spv::Scope S;
// Fill unknown synscope value to default Device scope.
if (!OCLStrMemScopeMap::find(SSIDs[ST->getSyncScopeID()].str(), &S)) {
S = ScopeDevice;
}

std::vector<Value *> Ops{ST->getPointerOperand(), getUInt32(M, S),
getUInt32(M, transAtomicOrdering(ST->getOrdering())),
ST->getValueOperand()};
std::vector<SPIRVValue *> SPIRVOps = transValue(Ops, BB);

return mapValue(ST, BM->addInstTemplate(OpAtomicStore, BM->getIds(SPIRVOps),
Expand All @@ -1746,9 +1751,15 @@ SPIRVValue *LLVMToSPIRVBase::transAtomicLoad(LoadInst *LD,
SPIRVBasicBlock *BB) {
SmallVector<StringRef> SSIDs;
LD->getContext().getSyncScopeNames(SSIDs);

spv::Scope S;
// Fill unknown synscope value to default Device scope.
if (!OCLStrMemScopeMap::find(SSIDs[LD->getSyncScopeID()].str(), &S)) {
S = ScopeDevice;
}

std::vector<Value *> Ops{
LD->getPointerOperand(),
getUInt32(M, map<Scope>(SSIDs[LD->getSyncScopeID()].str())),
LD->getPointerOperand(), getUInt32(M, S),
getUInt32(M, transAtomicOrdering(LD->getOrdering()))};
std::vector<SPIRVValue *> SPIRVOps = transValue(Ops, BB);

Expand Down Expand Up @@ -2316,7 +2327,13 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
// See the OpenCL C specification p6.13.11. "Atomic Functions"
SmallVector<StringRef> SSIDs;
ARMW->getContext().getSyncScopeNames(SSIDs);
Operands[1] = getUInt32(M, map<Scope>(SSIDs[ARMW->getSyncScopeID()].str()));

spv::Scope S;
// Fill unknown synscope value to default Device scope.
if (!OCLStrMemScopeMap::find(SSIDs[ARMW->getSyncScopeID()].str(), &S)) {
S = ScopeDevice;
}
Operands[1] = getUInt32(M, S);
Operands[2] = getUInt32(M, MemSem);
Operands[3] = ARMW->getValOperand();
std::vector<SPIRVValue *> OpVals = transValue(Operands, BB);
Expand Down
23 changes: 12 additions & 11 deletions test/transcoding/OpenCL/atomic_syncscope_test.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ target triple = "spir64"
; CHECK-SPIRV-DAG: Constant [[#]] [[#ConstInt1:]] 1
; CHECK-SPIRV-DAG: Constant [[#]] [[#ConstInt2:]] 2
; CHECK-SPIRV-DAG: Constant [[#]] [[#ConstInt3:]] 3
; CHECK-SPIRV-DAG: Constant [[#]] [[#ConstInt4:]] 4
; CHECK-SPIRV-DAG: Constant [[#]] [[#Const2Power30:]] 1073741824
; CHECK-SPIRV-DAG: Constant [[#]] [[#ConstInt42:]] 42

Expand Down Expand Up @@ -67,31 +68,31 @@ entry:
}

; Atomic* ResTypeId ResId PtrId MemScopeId MemSemanticsId ValueId
; CHECK-SPIRV: AtomicAnd [[#]] [[#]] [[#]] [[#ConstInt2]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicSMin [[#]] [[#]] [[#]] [[#ConstInt2]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicSMax [[#]] [[#]] [[#]] [[#ConstInt2]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicAnd [[#]] [[#]] [[#]] [[#ConstInt4]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicSMin [[#]] [[#]] [[#]] [[#ConstInt0]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicSMax [[#]] [[#]] [[#]] [[#ConstInt1]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicUMin [[#]] [[#]] [[#]] [[#ConstInt2]] [[#SequentiallyConsistent]] [[#ConstInt1]]
; CHECK-SPIRV: AtomicUMax [[#]] [[#]] [[#]] [[#ConstInt2]] [[#SequentiallyConsistent]] [[#ConstInt1]]

; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_and_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 1)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_min_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 1)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_max_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 1)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_and_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 0)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_min_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 3)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_max_explicitPU3AS4VU7_Atomicii12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 2)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_min_explicitPU3AS4VU7_Atomicjj12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 1)
; CHECK-LLVM: call spir_func i32 @_Z25atomic_fetch_max_explicitPU3AS4VU7_Atomicjj12memory_order12memory_scope(ptr{{.*}}, i32 1, i32 5, i32 1)

define dso_local void @fi3(ptr nocapture noundef %i, ptr nocapture noundef %ui) local_unnamed_addr #0 {
entry:
%0 = atomicrmw and ptr %i, i32 1 syncscope("workgroup") seq_cst, align 4
%1 = atomicrmw min ptr %i, i32 1 syncscope("workgroup") seq_cst, align 4
%2 = atomicrmw max ptr %i, i32 1 syncscope("workgroup") seq_cst, align 4
%0 = atomicrmw and ptr %i, i32 1 syncscope("work_item") seq_cst, align 4
%1 = atomicrmw min ptr %i, i32 1 syncscope("all_svm_devices") seq_cst, align 4
%2 = atomicrmw max ptr %i, i32 1 syncscope("wrong_scope") seq_cst, align 4
%3 = atomicrmw umin ptr %ui, i32 1 syncscope("workgroup") seq_cst, align 4
%4 = atomicrmw umax ptr %ui, i32 1 syncscope("workgroup") seq_cst, align 4
ret void
}

; AtomicCompareExchange ResTypeId ResId PtrId MemScopeId MemSemEqualId MemSemUnequalId ValueId ComparatorId
; CHECK-SPIRV: AtomicCompareExchange [[#]] [[#]] [[#]] [[#ConstInt1]] [[#ConstInt2]] [[#ConstInt2]] [[#ConstInt1]] [[#ConstInt0]]
; CHECK-LLVM: call spir_func i1 @_Z39atomic_compare_exchange_strong_explicitPU3AS4VU7_AtomiciPU3AS4ii12memory_orderS4_12memory_scope(ptr{{.*}}, ptr{{.*}}, i32 1, i32 2, i32 2, i32 2)
; CHECK-SPIRV: AtomicCompareExchange [[#]] [[#]] [[#]] [[#ConstInt2]] [[#ConstInt2]] [[#ConstInt2]] [[#ConstInt1]] [[#ConstInt0]]
; CHECK-LLVM: call spir_func i1 @_Z39atomic_compare_exchange_strong_explicitPU3AS4VU7_AtomiciPU3AS4ii12memory_orderS4_12memory_scope(ptr{{.*}}, ptr{{.*}}, i32 1, i32 2, i32 2, i32 1)

define dso_local zeroext i1 @fi4(ptr nocapture noundef %i) local_unnamed_addr #0 {
entry:
Expand Down

0 comments on commit a0c4f2e

Please sign in to comment.