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Fix check for (neg) zero for fpclass emulation #2151

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Fix check for (neg) zero for fpclass emulation #2151

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f8c2691
Fix check for (neg) zero for fpclass emulation
MrSidims Sep 8, 2023
b2e1148
Use compare
MrSidims Sep 8, 2023
244c7f6
Format
MrSidims Sep 8, 2023
355eb51
remove duplicated consts
MrSidims Sep 8, 2023
afe1796
format
MrSidims Sep 8, 2023
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31 changes: 23 additions & 8 deletions lib/SPIRV/SPIRVWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4436,15 +4436,30 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
// int float value
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auto *BitCastToInt =
BM->addUnaryInst(OpBitcast, OpSPIRVTy, InputFloat, BB);
auto *ZeroConst = transValue(
Constant::getIntegerValue(IntOpLLVMTy, APInt::getZero(BitSize)), BB);
auto *TestIsZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, ZeroConst, BB);
if (FPClass & fcPosZero && FPClass & fcNegZero)
APInt ZeroInt = APInt::getZero(BitSize);
auto *ZeroConst =
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@MrSidims MrSidims Sep 8, 2023 •
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mmm, actually, should also move them under if/else

transValue(Constant::getIntegerValue(IntOpLLVMTy, ZeroInt), BB);
ZeroInt.setSignBit();
auto *NegZeroConst =
transValue(Constant::getIntegerValue(IntOpLLVMTy, ZeroInt), BB);
if (FPClass & fcPosZero && FPClass & fcNegZero) {
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Instead of generating:

if (val==+0 || val==-0)

we might get better performance with:

if ((val&0x7fff...)==0)

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We need both val == 0 and val == -0 results. So, it is worthwhile to generate both.

Thanks

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I agree with @LU-JOHN 's suggestion; that should cover both cases.

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I think I might be missing something here. How will val & 0x&7fffffff give result for TestIsPosZero(..) and TestIsNegZero(..)? Is the idea here to replace val == 0 with (val & 0xFFFFFFFFF == 0) and val == -0 with (val && 0xFFFFFFFF != 0) && (val && 0x7FFFFFFF == 0)?
Can @svenvh or @LU-JOHN, please clarify? Thanks

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+0.0 is represented by 0x0000.0000 (for floats)
-0.0 is represented by 0x8000.0000 (for floats)
Instead of doing two tests we can check for both by doing:
(val & 0x7FFF.FFFF)==0x0000.0000

auto *TestIsPosZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, ZeroConst, BB);
auto *TestIsNegZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, NegZeroConst, BB);
auto *TestIsZero = BM->addInstTemplate(
OpLogicalOr, {TestIsPosZero->getId(), TestIsNegZero->getId()}, BB,
ResTy);
ResultVec.emplace_back(GetInvertedTestIfNeeded(TestIsZero));
else
ResultVec.emplace_back(GetInvertedTestIfNeeded(
GetNegPosInstTest(TestIsZero, FPClass & fcNegZero)));
} else if (FPClass & fcPosZero) {
auto *TestIsPosZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, ZeroConst, BB);
ResultVec.emplace_back(GetInvertedTestIfNeeded(TestIsPosZero));
} else {
auto *TestIsNegZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, NegZeroConst, BB);
ResultVec.emplace_back(GetInvertedTestIfNeeded(TestIsNegZero));
}
}
if (ResultVec.size() == 1)
return ResultVec.back();
Expand Down
26 changes: 11 additions & 15 deletions test/llvm-intrinsics/fpclass.ll
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Expand Up @@ -21,6 +21,7 @@
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#QNanBitConst:]] 2143289344
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#MantissaConst:]] 8388607
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#ZeroConst:]] 0
; CHECK-SPIRV-DAG: Constant [[#Int32Ty]] [[#NegatedZeroConst:]] 2147483648
; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#QNanBitConst64:]] 0 2146959360
; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#MantissaConst64:]] 4294967295 1048575
; CHECK-SPIRV-DAG: Constant [[#Int64Ty]] [[#ZeroConst64:]] 0 0
Expand Down Expand Up @@ -307,8 +308,10 @@ define i1 @test_class_zero(float %arg) {
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Equal]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#EqualPos:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#EqualNeg:]] [[#BitCast]] [[#NegatedZeroConst]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Result:]] [[#EqualPos]] [[#EqualNeg]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Result]]
%val = call i1 @llvm.is.fpclass.f32(float %arg, i32 96)
ret i1 %val
}
Expand All @@ -320,11 +323,8 @@ define i1 @test_class_poszero(float %arg) {
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: SignBitSet [[#BoolTy]] [[#Sign:]] [[#Val]]
; CHECK-SPIRV-NEXT: LogicalNot [[#BoolTy]] [[#Not:]] [[#Sign]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And:]] [[#Not]] [[#Equal]]
; CHECK-SPIRV-NEXT: ReturnValue [[#And]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Equal]]
%val = call i1 @llvm.is.fpclass.f32(float %arg, i32 64)
ret i1 %val
}
Expand All @@ -336,10 +336,8 @@ define i1 @test_class_negzero(float %arg) {
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: SignBitSet [[#BoolTy]] [[#Sign:]] [[#Val]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And:]] [[#Sign]] [[#Equal]]
; CHECK-SPIRV-NEXT: ReturnValue [[#And]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#NegatedZeroConst]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Equal]]
%val = call i1 @llvm.is.fpclass.f32(float %arg, i32 32)
ret i1 %val
}
Expand Down Expand Up @@ -383,11 +381,10 @@ define i1 @test_class_neginf_posnormal_negsubnormal_poszero_snan_f64(double %arg
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And4:]] [[#Sign]] [[#Less]]
; CHECK-SPIRV-NEXT: Bitcast [[#Int64Ty]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast3]] [[#ZeroConst64]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And5:]] [[#Not2]] [[#Equal]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or1:]] [[#And1]] [[#And2]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or2:]] [[#Or1]] [[#And3]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or3:]] [[#Or2]] [[#And4]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or4:]] [[#Or3]] [[#And5]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or4:]] [[#Or3]] [[#Equal]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Or4]]
%val = call i1 @llvm.is.fpclass.f64(double %arg, i32 341)
ret i1 %val
Expand Down Expand Up @@ -416,11 +413,10 @@ define <2 x i1> @test_class_neginf_posnormal_negsubnormal_poszero_snan_v2f16(<2
; CHECK-SPIRV-NEXT: LogicalAnd [[#VecBoolTy]] [[#And4:]] [[#Sign]] [[#Less]]
; CHECK-SPIRV-NEXT: Bitcast [[#Int16VecTy]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#VecBoolTy]] [[#Equal:]] [[#BitCast3]] [[#ZeroConst16]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#VecBoolTy]] [[#And5:]] [[#Not2]] [[#Equal]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or1:]] [[#And1]] [[#And2]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or2:]] [[#Or1]] [[#And3]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or3:]] [[#Or2]] [[#And4]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or4:]] [[#Or3]] [[#And5]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or4:]] [[#Or3]] [[#Equal]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Or4]]
%val = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %arg, i32 341)
ret <2 x i1> %val
Expand Down
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