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Fix check for (neg) zero for fpclass emulation #2151

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Fix check for (neg) zero for fpclass emulation #2151

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f8c2691
Fix check for (neg) zero for fpclass emulation
MrSidims Sep 8, 2023
b2e1148
Use compare
MrSidims Sep 8, 2023
244c7f6
Format
MrSidims Sep 8, 2023
355eb51
remove duplicated consts
MrSidims Sep 8, 2023
afe1796
format
MrSidims Sep 8, 2023
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8 changes: 4 additions & 4 deletions lib/SPIRV/SPIRVWriter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4432,14 +4432,14 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
GetNegPosInstTest(TestIsSubnormal, FPClass & fcNegSubnormal)));
}
if (FPClass & fcZero) {
// Create zero integer constant and check for equality with bitcasted to
// Create zero integer constant and check for equality with converted to
// int float value
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auto *BitCastToInt =
BM->addUnaryInst(OpBitcast, OpSPIRVTy, InputFloat, BB);
auto *Convert =
BM->addUnaryInst(OpConvertFToU, OpSPIRVTy, InputFloat, BB);
auto *ZeroConst = transValue(
Constant::getIntegerValue(IntOpLLVMTy, APInt::getZero(BitSize)), BB);
auto *TestIsZero =
BM->addCmpInst(OpIEqual, ResTy, BitCastToInt, ZeroConst, BB);
BM->addCmpInst(OpIEqual, ResTy, Convert, ZeroConst, BB);
if (FPClass & fcPosZero && FPClass & fcNegZero)
ResultVec.emplace_back(GetInvertedTestIfNeeded(TestIsZero));
else
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12 changes: 6 additions & 6 deletions test/llvm-intrinsics/fpclass.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,7 @@ define i1 @test_class_zero(float %arg) {
; CHECK-SPIRV-NEXT: FunctionParameter [[#]] [[#Val:]]
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: ConvertFToU [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: ReturnValue [[#Equal]]
%val = call i1 @llvm.is.fpclass.f32(float %arg, i32 96)
Expand All @@ -319,8 +319,8 @@ define i1 @test_class_poszero(float %arg) {
; CHECK-SPIRV-NEXT: FunctionParameter [[#]] [[#Val:]]
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: ConvertFToU [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: SignBitSet [[#BoolTy]] [[#Sign:]] [[#Val]]
; CHECK-SPIRV-NEXT: LogicalNot [[#BoolTy]] [[#Not:]] [[#Sign]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And:]] [[#Not]] [[#Equal]]
Expand All @@ -335,7 +335,7 @@ define i1 @test_class_negzero(float %arg) {
; CHECK-SPIRV-NEXT: FunctionParameter [[#]] [[#Val:]]
; CHECK-SPIRV-EMPTY:
; CHECK-SPIRV-NEXT: Label
; CHECK-SPIRV-NEXT: Bitcast [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: ConvertFToU [[#Int32Ty]] [[#BitCast:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast]] [[#ZeroConst]]
; CHECK-SPIRV-NEXT: SignBitSet [[#BoolTy]] [[#Sign:]] [[#Val]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And:]] [[#Sign]] [[#Equal]]
Expand Down Expand Up @@ -381,7 +381,7 @@ define i1 @test_class_neginf_posnormal_negsubnormal_poszero_snan_f64(double %arg
; CHECK-SPIRV-NEXT: ISub [[#Int64Ty]] [[#Sub:]] [[#BitCast2]] [[#MantissaConst64]]
; CHECK-SPIRV-NEXT: ULessThan [[#BoolTy]] [[#Less:]] [[#Sub]] [[#MantissaConst64]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And4:]] [[#Sign]] [[#Less]]
; CHECK-SPIRV-NEXT: Bitcast [[#Int64Ty]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: ConvertFToU [[#Int64Ty]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#BoolTy]] [[#Equal:]] [[#BitCast3]] [[#ZeroConst64]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#BoolTy]] [[#And5:]] [[#Not2]] [[#Equal]]
; CHECK-SPIRV-NEXT: LogicalOr [[#BoolTy]] [[#Or1:]] [[#And1]] [[#And2]]
Expand Down Expand Up @@ -414,7 +414,7 @@ define <2 x i1> @test_class_neginf_posnormal_negsubnormal_poszero_snan_v2f16(<2
; CHECK-SPIRV-NEXT: ISub [[#Int16VecTy]] [[#Sub:]] [[#BitCast2]] [[#MantissaConstVec16]]
; CHECK-SPIRV-NEXT: ULessThan [[#VecBoolTy]] [[#Less:]] [[#Sub]] [[#MantissaConstVec16]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#VecBoolTy]] [[#And4:]] [[#Sign]] [[#Less]]
; CHECK-SPIRV-NEXT: Bitcast [[#Int16VecTy]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: ConvertFToU [[#Int16VecTy]] [[#BitCast3:]] [[#Val]]
; CHECK-SPIRV-NEXT: IEqual [[#VecBoolTy]] [[#Equal:]] [[#BitCast3]] [[#ZeroConst16]]
; CHECK-SPIRV-NEXT: LogicalAnd [[#VecBoolTy]] [[#And5:]] [[#Not2]] [[#Equal]]
; CHECK-SPIRV-NEXT: LogicalOr [[#VecBoolTy]] [[#Or1:]] [[#And1]] [[#And2]]
Expand Down
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