Merge branch 'master' of https://git.openjdk.org/jdk into JDK-8234502

.jcheck/conf

@@ -1,7 +1,7 @@
 [general]
 project=jdk
 jbs=JDK
-version=22
+version=23
 
 [checks]
 error=author,committer,reviewers,merge,issues,executable,symlink,message,hg-tag,whitespace,problemlists

make/CompileInterimLangtools.gmk

@@ -99,6 +99,9 @@ define SetupInterimModule
  EXCLUDE_FILES := $(TOPDIR)/src/$1/share/classes/module-info.java \
  $(TOPDIR)/src/$1/share/classes/javax/tools/ToolProvider.java \
  $(TOPDIR)/src/$1/share/classes/com/sun/tools/javac/launcher/Main.java \
+ $(TOPDIR)/src/$1/share/classes/com/sun/tools/javac/launcher/MemoryContext.java \
+ $(TOPDIR)/src/$1/share/classes/com/sun/tools/javac/launcher/MemoryModuleFinder.java \
+ $(TOPDIR)/src/$1/share/classes/com/sun/tools/javac/launcher/SourceLauncher.java \
  Standard.java, \
  EXTRA_FILES := $(BUILDTOOLS_OUTPUTDIR)/gensrc/$1.interim/module-info.java \
  $($1.interim_EXTRA_FILES), \

make/autoconf/basic_tools.m4

@@ -390,6 +390,17 @@ AC_DEFUN_ONCE([BASIC_SETUP_COMPLEX_TOOLS],
 
  if test "x$OPENJDK_TARGET_OS" = "xmacosx"; then
  UTIL_REQUIRE_PROGS(DSYMUTIL, dsymutil)
+ AC_MSG_CHECKING([if dsymutil supports --reproducer option])
+ if $DSYMUTIL --help | $GREP -q '\--reproducer '; then
+ AC_MSG_RESULT([yes])
+ # --reproducer option is supported
+ # set "--reproducer Off" to prevent unnecessary temporary
+ # directories creation
+ DSYMUTIL="$DSYMUTIL --reproducer Off"
+ else
+ # --reproducer option isn't supported
+ AC_MSG_RESULT([no])
+ fi
  UTIL_REQUIRE_PROGS(MIG, mig)
  UTIL_REQUIRE_PROGS(XATTR, xattr)
  UTIL_LOOKUP_PROGS(CODESIGN, codesign)

make/conf/version-numbers.conf

@@ -26,17 +26,17 @@
 # Default version, product, and vendor information to use,
 # unless overridden by configure
 
-DEFAULT_VERSION_FEATURE=22
+DEFAULT_VERSION_FEATURE=23
 DEFAULT_VERSION_INTERIM=0
 DEFAULT_VERSION_UPDATE=0
 DEFAULT_VERSION_PATCH=0
 DEFAULT_VERSION_EXTRA1=0
 DEFAULT_VERSION_EXTRA2=0
 DEFAULT_VERSION_EXTRA3=0
-DEFAULT_VERSION_DATE=2024-03-19
-DEFAULT_VERSION_CLASSFILE_MAJOR=66 # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`"
+DEFAULT_VERSION_DATE=2024-09-17
+DEFAULT_VERSION_CLASSFILE_MAJOR=67 # "`$EXPR $DEFAULT_VERSION_FEATURE + 44`"
 DEFAULT_VERSION_CLASSFILE_MINOR=0
 DEFAULT_VERSION_DOCS_API_SINCE=11
-DEFAULT_ACCEPTABLE_BOOT_VERSIONS="21 22"
-DEFAULT_JDK_SOURCE_TARGET_VERSION=22
+DEFAULT_ACCEPTABLE_BOOT_VERSIONS="21 22 23"
+DEFAULT_JDK_SOURCE_TARGET_VERSION=23
 DEFAULT_PROMOTED_VERSION_PRE=ea

make/jdk/src/classes/build/tools/module/GenModuleInfoSource.java

@@ -473,6 +473,11 @@ private void process(Parser parser, boolean extraFile) throws IOException {
  if (parser.peekToken() != null) { // must be EOF
  throw parser.newError("is malformed");
  }
+ } else if (token.equals("import")) {
+ nextIdentifier(parser);
+ skipTokenOrThrow(parser, ";", "missing semicolon");
+ } else if (token.startsWith("@")) {
+ continue;
  } else {
  throw parser.newError("missing keyword");
  }

make/modules/java.base/Java.gmk

@@ -36,8 +36,8 @@ EXCLUDE_FILES += \
  $(TOPDIR)/src/java.base/share/classes/jdk/internal/module/ModuleLoaderMap.java
 
 EXCLUDES += java/lang/doc-files \
- jdk/internal/classfile/snippet-files \
- jdk/internal/classfile/components/snippet-files
+ java/lang/classfile/snippet-files \
+ java/lang/classfile/components/snippet-files
 
 # Exclude BreakIterator classes that are just used in compile process to generate
 # data files and shouldn't go in the product

make/modules/jdk.compiler/Gendata.gmk

@@ -42,6 +42,9 @@ CT_MODULES_API_TARGETS := \
  $(foreach m, $(CT_MODULES) $(CT_TRANSITIVE_MODULES), \
  $(call SetupJavaCompilationApiTarget, $m, $(JDK_OUTPUTDIR)/modules/$m))
 
+#undocumented modules which should also be included in ct.sym:
+CT_EXTRA_MODULES := jdk.unsupported
+
 SYMBOL_FILES := $(wildcard $(MODULE_SRC)/share/data/symbols/*)
 
 CT_DATA_DESCRIPTION += $(MODULE_SRC)/share/data/symbols/symbols
@@ -72,6 +75,7 @@ $(SUPPORT_OUTPUTDIR)/symbols/ct.sym: $(COMPILE_CREATE_SYMBOLS) $(SYMBOL_FILES) \
  $(RM) -r $(@D)
  $(MKDIR) -p $(@D)
  $(ECHO) Creating ct.sym classes
+ $(ECHO) $(CT_MODULES) $(CT_TRANSITIVE_MODULES) $(CT_EXTRA_MODULES) >$(SUPPORT_OUTPUTDIR)/symbols/included-modules
  $(BUILD_JAVA_SMALL) \
  $(COMPILECREATESYMBOLS_ADD_EXPORTS) \
  -classpath $(BUILDTOOLS_OUTPUTDIR)/create_symbols_javac \
@@ -82,7 +86,8 @@ $(SUPPORT_OUTPUTDIR)/symbols/ct.sym: $(COMPILE_CREATE_SYMBOLS) $(SYMBOL_FILES) \
  $(SOURCE_DATE_EPOCH) \
  $(JDK_SOURCE_TARGET_VERSION) \
  "$(VERSION_PRE)" \
- $(JDK_OUTPUTDIR)/modules/
+ $(JDK_OUTPUTDIR)/modules/ \
+ $(SUPPORT_OUTPUTDIR)/symbols/included-modules
  $(TOUCH) $@
 
 # Copy ct.sym to the modules libs dir

make/src/classes/build/tools/jfr/GenerateJfrFiles.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2018, 2023, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
@@ -198,6 +198,7 @@ static class TypeElement {
  String period = "";
  boolean cutoff;
  boolean throttle;
+ String level = "";
  boolean experimental;
  boolean internal;
  long id;
@@ -222,6 +223,7 @@ public void persist(DataOutputStream pos) throws IOException {
  pos.writeUTF(period);
  pos.writeBoolean(cutoff);
  pos.writeBoolean(throttle);
+ pos.writeUTF(level);
  pos.writeBoolean(experimental);
  pos.writeBoolean(internal);
  pos.writeLong(id);
@@ -520,6 +522,7 @@ public void startElement(String uri, String localName, String qName, Attributes
  currentType.startTime = getBoolean(attributes, "startTime", true);
  currentType.period = getString(attributes, "period");
  currentType.cutoff = getBoolean(attributes, "cutoff", false);
+ currentType.level = getString(attributes, "level");
  currentType.throttle = getBoolean(attributes, "throttle", false);
  currentType.commitState = getString(attributes, "commitState");
  currentType.isEvent = "Event".equals(qName);
@@ -651,7 +654,7 @@ private static void printJfrEventControlHpp(Metadata metadata, File outputFile)
  out.write("");
  out.write("struct jfrNativeEventSetting {");
  out.write(" jlong threshold_ticks;");
- out.write(" jlong cutoff_ticks;");
+ out.write(" jlong miscellaneous;");
  out.write(" u1 stacktrace;");
  out.write(" u1 enabled;");
  out.write(" u1 large;");

make/test/BuildMicrobenchmark.gmk

@@ -98,11 +98,6 @@ $(eval $(call SetupJavaCompilation, BUILD_JDK_MICROBENCHMARK, \
  BIN := $(MICROBENCHMARK_CLASSES), \
  JAVAC_FLAGS := --add-exports java.base/sun.security.util=ALL-UNNAMED \
  --add-exports java.base/sun.invoke.util=ALL-UNNAMED \
- --add-exports java.base/jdk.internal.classfile=ALL-UNNAMED \
- --add-exports java.base/jdk.internal.classfile.attribute=ALL-UNNAMED \
- --add-exports java.base/jdk.internal.classfile.constantpool=ALL-UNNAMED \
- --add-exports java.base/jdk.internal.classfile.instruction=ALL-UNNAMED \
- --add-exports java.base/jdk.internal.classfile.components=ALL-UNNAMED \
  --add-exports java.base/jdk.internal.classfile.impl=ALL-UNNAMED \
  --add-exports java.base/jdk.internal.org.objectweb.asm=ALL-UNNAMED \
  --add-exports java.base/jdk.internal.org.objectweb.asm.tree=ALL-UNNAMED \

src/hotspot/cpu/aarch64/aarch64_vector.ad

@@ -3742,6 +3742,68 @@ instruct reinterpret_resize_gt128b(vReg dst, vReg src, pReg ptmp, rFlagsReg cr)
  ins_pipe(pipe_slow);
 %}
 
+// ---------------------------- Vector zero extend --------------------------------
+
+instruct vzeroExtBtoX(vReg dst, vReg src) %{
+ match(Set dst (VectorUCastB2X src));
+ format %{ "vzeroExtBtoX $dst, $src" %}
+ ins_encode %{
+ BasicType bt = Matcher::vector_element_basic_type(this);
+ assert(bt == T_SHORT || bt == T_INT || bt == T_LONG, "must be");
+ uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+ if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+ // 4B to 4S/4I, 8B to 8S
+ __ neon_vector_extend($dst$$FloatRegister, bt, length_in_bytes,
+ $src$$FloatRegister, T_BYTE, /* is_unsigned */ true);
+ } else {
+ assert(UseSVE > 0, "must be sve");
+ __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt),
+ $src$$FloatRegister, __ B, /* is_unsigned */ true);
+ }
+ %}
+ ins_pipe(pipe_slow);
+%}
+
+instruct vzeroExtStoX(vReg dst, vReg src) %{
+ match(Set dst (VectorUCastS2X src));
+ format %{ "vzeroExtStoX $dst, $src" %}
+ ins_encode %{
+ BasicType bt = Matcher::vector_element_basic_type(this);
+ assert(bt == T_INT || bt == T_LONG, "must be");
+ uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+ if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+ // 4S to 4I
+ __ neon_vector_extend($dst$$FloatRegister, T_INT, length_in_bytes,
+ $src$$FloatRegister, T_SHORT, /* is_unsigned */ true);
+ } else {
+ assert(UseSVE > 0, "must be sve");
+ __ sve_vector_extend($dst$$FloatRegister, __ elemType_to_regVariant(bt),
+ $src$$FloatRegister, __ H, /* is_unsigned */ true);
+ }
+ %}
+ ins_pipe(pipe_slow);
+%}
+
+instruct vzeroExtItoX(vReg dst, vReg src) %{
+ match(Set dst (VectorUCastI2X src));
+ format %{ "vzeroExtItoX $dst, $src" %}
+ ins_encode %{
+ BasicType bt = Matcher::vector_element_basic_type(this);
+ assert(bt == T_LONG, "must be");
+ uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+ if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+ // 2I to 2L
+ __ neon_vector_extend($dst$$FloatRegister, T_LONG, length_in_bytes,
+ $src$$FloatRegister, T_INT, /* is_unsigned */ true);
+ } else {
+ assert(UseSVE > 0, "must be sve");
+ __ sve_vector_extend($dst$$FloatRegister, __ D,
+ $src$$FloatRegister, __ S, /* is_unsigned */ true);
+ }
+ %}
+ ins_pipe(pipe_slow);
+%}
+
 // ------------------------------ Vector cast ----------------------------------
 
 // VectorCastB2X

src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

@@ -2276,6 +2276,33 @@ instruct reinterpret_resize_gt128b(vReg dst, vReg src, pReg ptmp, rFlagsReg cr)
  ins_pipe(pipe_slow);
 %}
 
+// ---------------------------- Vector zero extend --------------------------------
+dnl VECTOR_ZERO_EXTEND($1, $2, $3, $4, $5 $6, $7, )
+dnl VECTOR_ZERO_EXTEND(op_name, dst_bt, src_bt, dst_size, src_size, assertion, neon_comment)
+define(`VECTOR_ZERO_EXTEND', `
+instruct vzeroExt$1toX(vReg dst, vReg src) %{
+ match(Set dst (VectorUCast`$1'2X src));
+ format %{ "vzeroExt$1toX $dst, $src" %}
+ ins_encode %{
+ BasicType bt = Matcher::vector_element_basic_type(this);
+ assert($6, "must be");
+ uint length_in_bytes = Matcher::vector_length_in_bytes(this);
+ if (VM_Version::use_neon_for_vector(length_in_bytes)) {
+ // $7
+ __ neon_vector_extend($dst$$FloatRegister, $2, length_in_bytes,
+ $src$$FloatRegister, $3, /* is_unsigned */ true);
+ } else {
+ assert(UseSVE > 0, "must be sve");
+ __ sve_vector_extend($dst$$FloatRegister, __ $4,
+ $src$$FloatRegister, __ $5, /* is_unsigned */ true);
+ }
+ %}
+ ins_pipe(pipe_slow);
+%}')dnl
+VECTOR_ZERO_EXTEND(B, bt, T_BYTE, elemType_to_regVariant(bt), B, bt == T_SHORT || bt == T_INT || bt == T_LONG, `4B to 4S/4I, 8B to 8S')
+VECTOR_ZERO_EXTEND(S, T_INT, T_SHORT, elemType_to_regVariant(bt), H, bt == T_INT || bt == T_LONG, `4S to 4I')
+VECTOR_ZERO_EXTEND(I, T_LONG, T_INT, D, S, bt == T_LONG, `2I to 2L')
+
 // ------------------------------ Vector cast ----------------------------------
 
 // VectorCastB2X

src/hotspot/cpu/aarch64/assembler_aarch64.hpp

@@ -2196,41 +2196,20 @@ void mvnw(Register Rd, Register Rm,
 
 #undef INSN
 
- enum sign_kind { SIGNED, UNSIGNED };
-
 private:
- void _xcvtf_scalar_integer(sign_kind sign, unsigned sz,
- FloatRegister Rd, FloatRegister Rn) {
- starti;
- f(0b01, 31, 30), f(sign == SIGNED ? 0 : 1, 29);
- f(0b111100, 27, 23), f((sz >> 1) & 1, 22), f(0b100001110110, 21, 10);
- rf(Rn, 5), rf(Rd, 0);
- }
-
-public:
-#define INSN(NAME, sign, sz) \
- void NAME(FloatRegister Rd, FloatRegister Rn) { \
- _xcvtf_scalar_integer(sign, sz, Rd, Rn); \
- }
-
- INSN(scvtfs, SIGNED, 0);
- INSN(scvtfd, SIGNED, 1);
-
-#undef INSN
-
-private:
- void _xcvtf_vector_integer(sign_kind sign, SIMD_Arrangement T,
+ void _xcvtf_vector_integer(bool is_unsigned, SIMD_Arrangement T,
  FloatRegister Rd, FloatRegister Rn) {
  assert(T == T2S || T == T4S || T == T2D, "invalid arrangement");
  starti;
- f(0, 31), f(T & 1, 30), f(sign == SIGNED ? 0 : 1, 29);
+ f(0, 31), f(T & 1, 30), f(is_unsigned ? 1 : 0, 29);
  f(0b011100, 28, 23), f((T >> 1) & 1, 22), f(0b100001110110, 21, 10);
  rf(Rn, 5), rf(Rd, 0);
  }
 
 public:
+
  void scvtfv(SIMD_Arrangement T, FloatRegister Rd, FloatRegister Rn) {
- _xcvtf_vector_integer(SIGNED, T, Rd, Rn);
+ _xcvtf_vector_integer(/* is_unsigned */ false, T, Rd, Rn);
  }
 
  // Floating-point compare
@@ -2991,8 +2970,8 @@ template<typename R, typename... Rx>
 
 #undef INSN
 
-private:
- void _xshll(sign_kind sign, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
+protected:
+ void _xshll(bool is_unsigned, FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
  starti;
  /* The encodings for the immh:immb fields (bits 22:16) are
  * 0001 xxx 8H, 8B/16B shift = xxx
@@ -3002,20 +2981,20 @@ template<typename R, typename... Rx>
  */
  assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
  assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
- f(0, 31), f(Tb & 1, 30), f(sign == SIGNED ? 0 : 1, 29), f(0b011110, 28, 23);
+ f(0, 31), f(Tb & 1, 30), f(is_unsigned ? 1 : 0, 29), f(0b011110, 28, 23);
  f((1 << ((Tb>>1)+3))|shift, 22, 16);
  f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
  }
 
 public:
  void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
  assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
- _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
+ _xshll(/* is_unsigned */ true, Vd, Ta, Vn, Tb, shift);
  }
 
  void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
  assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
- _xshll(UNSIGNED, Vd, Ta, Vn, Tb, shift);
+ _xshll(/* is_unsigned */ true, Vd, Ta, Vn, Tb, shift);
  }
 
  void uxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
@@ -3024,12 +3003,12 @@ template<typename R, typename... Rx>
 
  void sshll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
  assert(Tb == T8B || Tb == T4H || Tb == T2S, "invalid arrangement");
- _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
+ _xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
  }
 
  void sshll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
  assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
- _xshll(SIGNED, Vd, Ta, Vn, Tb, shift);
+ _xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
  }
 
  void sxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
@@ -3862,18 +3841,25 @@ template<typename R, typename... Rx>
  }
 
 // SVE unpack vector elements
-#define INSN(NAME, op) \
- void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) { \
- starti; \
- assert(T != B && T != Q, "invalid size"); \
- f(0b00000101, 31, 24), f(T, 23, 22), f(0b1100, 21, 18); \
- f(op, 17, 16), f(0b001110, 15, 10), rf(Zn, 5), rf(Zd, 0); \
+protected:
+ void _sve_xunpk(bool is_unsigned, bool is_high, FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) {
+ starti;
+ assert(T != B && T != Q, "invalid size");
+ f(0b00000101, 31, 24), f(T, 23, 22), f(0b1100, 21, 18);
+ f(is_unsigned ? 1 : 0, 17), f(is_high ? 1 : 0, 16),
+ f(0b001110, 15, 10), rf(Zn, 5), rf(Zd, 0);
+ }
+
+public:
+#define INSN(NAME, is_unsigned, is_high) \
+ void NAME(FloatRegister Zd, SIMD_RegVariant T, FloatRegister Zn) { \
+ _sve_xunpk(is_unsigned, is_high, Zd, T, Zn); \
  }
 
- INSN(sve_uunpkhi, 0b11); // Signed unpack and extend half of vector - high half
- INSN(sve_uunpklo, 0b10); // Signed unpack and extend half of vector - low half
- INSN(sve_sunpkhi, 0b01); // Unsigned unpack and extend half of vector - high half
- INSN(sve_sunpklo, 0b00); // Unsigned unpack and extend half of vector - low half
+ INSN(sve_uunpkhi, true, true ); // Unsigned unpack and extend half of vector - high half
+ INSN(sve_uunpklo, true, false); // Unsigned unpack and extend half of vector - low half
+ INSN(sve_sunpkhi, false, true ); // Signed unpack and extend half of vector - high half
+ INSN(sve_sunpklo, false, false); // Signed unpack and extend half of vector - low half
 #undef INSN
 
 // SVE unpack predicate elements