Merge 3118272 into 128c19a

Makefile

@@ -15,10 +15,10 @@ yosys/yosys:
 run: cgploss.so
 	yosys/yosys -m cgploss.so
 
-tests: cgploss.so
-	@echo "[info] starting implementation tests"
+test: cgploss.so
+	@echo "[info] starting implementation test $(dir)"
 	@EXIT_CODE=0
-	for f in ./tests/*; do \
+	for f in ./tests/$(dir); do \
 		if [ -d "$$f" -a $$(echo -n "$$f" | tail -c 1) != "-" -a $$(echo -n "$$f" | tail -c 4) != "unit" ]; then \
 			#echo "$$f STARTED" && \
 			yosys/yosys -m cgploss.so < "$$f/run" > test_run.txt || { echo -e "$$f \e[31mFAILED\e[0m" ; EXIT_CODE=1; continue; } && \
@@ -35,35 +35,14 @@ tests: cgploss.so
 		fi \
 	done
 	# remove tests outputs
-	rm -f test_design
-	rm -f test_run.txt
-	rm -f test_out.v
-	@echo "[info] implementation tests done"
+	@echo "[info] implementation test $(dir) done"
 	@exit $$EXIT_CODE
 
-stop-tests: cgploss.so
-	@echo "[info] starting implementation tests"
-	for f in ./tests/*; do \
-		if [ -d "$$f" -a $$(echo -n "$$f" | tail -c 1) != "-" -a $$(echo -n "$$f" | tail -c 4) != "unit" ]; then \
-			#echo "$$f STARTED" && \
-			yosys/yosys -m cgploss.so < "$$f/run" > test_run.txt || { echo -e "$$f \e[31mFAILED\e[0m" ; exit 1; } && \
-			iverilog -o test_design test_out.v "$$f/tb.v" || { echo -e "$$f \e[31mFAILED\e[0m" ; exit 1; } && \
-			vvp test_design || { echo -e "$$f \e[31mFAILED\e[0m" ; exit 1; } && \
-			echo -e "$$f \e[32mPASS\e[0m"; \
-		elif [ -d "$$f" -a $$(echo -n "$$f" | tail -c 1) != "-" -a $$(echo -n "$$f" | tail -c 4) == "unit" ]; then \
-			#echo "$$f STARTED UNIT TEST" && \
-			cp $$f/test.cpp src/test.cpp  && \
-			yosys/yosys-config --exec --cxx --cxxflags --ldflags -o cgplossUnit.so -shared $(TEST_SRC) -I yosys/ -I include/ --ldlibs > test_run.txt 2>&1 || { echo -e "$$f \e[31mFAILED\e[0m" ; exit 1; } && \
-			rm -f src/test.cpp && \
-			yosys/yosys -m cgplossUnit.so < "$$f/run" >> test_run.txt || { echo -e "$$f \e[31mFAILED\e[0m" ; exit 1; } && \
-			echo -e "$$f \e[32mPASS\e[0m"; \
-		fi \
-	done
-	# remove tests outputs
+tests:
+	make test dir=*
 	rm -f test_design
 	rm -f test_run.txt
 	rm -f test_out.v
-	@echo "[info] implementation tests done"
 
 clean:
 	rm -f cgploss.so

README.md

@@ -1,6 +1,6 @@
-# CGP Loss optimalization YOSYS extension
+# CGP Loss optimalization YOSYS extension (CGP Aproximation)
 
-use genetic algoritms for optimalize circuics with accepted error on output or without it.
+Use genetic algoritms for optimalize/aproximate circuics with accepted error on output or without it. This tool was created as a part of bachelor thesis at BUT FIT, this thesis is available at https://www.fit.vut.cz/study/thesis/22357/ .
 
 
 ## Getting Started
@@ -100,7 +100,7 @@ make tests
 cgploss.so       build cgploss extension (default)
 multicore        build cgploss extension with multicore support
 tests            run tests
-stop-tests       run tests when fail stops
+test dir=name    start test with name
 yosys/yosys      build yosys submodule
 run              run yosys with extension
 clean            clean repo

include/about.h

@@ -9,7 +9,7 @@
 namespace about {
 
     const std::string name           = "cgploss";
-    const unsigned    version        = 1;
+    const unsigned    version        = 2;
     const std::string authors        = "Lukas Plevac <xpleva07@vutbr.cz, lukas@plevac.eu>";
     const std::string build_time     = __DATE__ " " __TIME__;
     const int         optimalization = __OPTIMIZE_SIZE__;

include/config-parse.h

@@ -20,9 +20,9 @@ namespace config {
 			/**
 			 * @brief Return weight of port
 			 * @param port SigBit of port
-			 * @return unsigned weight
+			 * @return float weight
 			 */
-			unsigned port_weight(Yosys::RTLIL::SigBit &port);
+			float port_weight(Yosys::RTLIL::SigBit &port);
 
 			/**
 			 * @brief Parse file with port weights specifications

include/simulation.h

@@ -74,8 +74,8 @@ namespace simulation {
 	 * @param xor_outputs xor between reference and individual output
 	 * @param rtl_ports  map between chromozome index and RTLIL SigBit
 	 * @param config_parse config parser with port weights
-	 * @return unsigned maximal error
+	 * @return float maximal error
 	 */
-	unsigned one_max_loss(std::vector<io_t> xor_outputs, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> rtl_ports, config::parse *config_parse);
+	float one_max_loss(std::vector<io_t> xor_outputs, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> rtl_ports, config::parse *config_parse);
 
 }

include/types.h

@@ -0,0 +1,62 @@
+/**
+ * yosys-cgploss - Create circuics using Genetic (CGP)
+ * support data types header file
+ * @author Lukas Plevac <xpleva07@vutbr.cz>
+ */
+
+#pragma once
+
+namespace types {
+	/**
+	 * @brief Reprezenting number as 2**exp
+	 */
+	class Exponent {
+		public:
+			/**
+			 * @brief Exponent of reprezented number
+			 */
+			unsigned exp;
+
+			Exponent(unsigned exponent) {
+				this->exp = exponent;
+			}
+
+			Exponent() {
+				this->exp = 0;
+			}
+
+			/**
+			 * Get real value of number
+			 * @return unsigned
+			 */
+			unsigned real() {
+				return 1 << this->exp;			
+			}
+
+			Exponent operator*(const Exponent& b) {
+				Exponent c(this->exp);
+				c.exp += b.exp;
+				return c;
+      			}
+
+			Exponent operator/(const Exponent& b) {
+				Exponent c(this->exp);
+				c.exp -= b.exp;
+				return c;	
+      			}
+
+
+			friend float operator/(const float& lhs, const Exponent& rhs) {
+				unsigned do_div = rhs.exp;
+				float out = lhs;
+
+				while (do_div) {
+					out = out / 2;
+					do_div--;
+				}
+
+				return out;
+			}
+
+	};
+}

src/config-parse.cpp

@@ -7,6 +7,7 @@
 
 #include "config-parse.h"
 #include <algorithm>
+#include <math.h>
 
 namespace config {
     unsigned parse::parse_file(std::ifstream &config_file, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> &rtl_ports) {
@@ -35,15 +36,15 @@ namespace config {
 		return true;
     }
 
-    unsigned parse::port_weight(Yosys::RTLIL::SigBit &port) {
+    float parse::port_weight(Yosys::RTLIL::SigBit &port) {
         if (this->ports.count(port.wire->name.str()) != 0) {
             if ((int) this->ports[port.wire->name.str()].size() > port.offset) {
 		        return this->ports[port.wire->name.str()][port.offset];
             }
 	    }
 
         //default for unknew
-        return 1 << port.offset;
+        return exp2(port.offset);
     }
 
     unsigned parse::wire_bits(const std::string& name, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> &rtl_ports) {

src/generation.cpp

@@ -6,6 +6,7 @@
 
 
 #include "generation.h"
+#include "types.h"
 #include <random>
 #include <algorithm>
 
@@ -81,7 +82,8 @@ namespace evolution {
 
 		this->individuals[index].mae = 0;
 		this->individuals[index].wce = 0;
-		unsigned variants_count      = 1 << TO_REAL_INPUT(this->individuals[index].repres->chromosome->last_input + 1);
+		types::Exponent variants_count(TO_REAL_INPUT(this->individuals[index].repres->chromosome->last_input + 1));
+		unsigned        variants_count_sim  = (ONE_SIM_VARIANTS >= variants_count.exp) ? 1 <<  variants_count.exp : 1 << ONE_SIM_VARIANTS;
 
 		std::vector<simulation::io_t> xor_outputs(this->individuals[index].repres->chromosome->wire_out.size());
 		std::vector<simulation::io_t> test_circuic(this->individuals[index].repres->chromosome->size());
@@ -100,10 +102,10 @@ namespace evolution {
 			SET_VARIANTS_BITS(reference_circuic[i].vec, TO_REAL_INPUT(i));
 		}
 
-		unsigned total_error = 0;
+		float total_error = 0;
 		bool done = false;
 
-		if (ONE_SIM_VARIANTS > TO_REAL_INPUT(this->individuals[index].repres->chromosome->last_input + 1)) {
+		if (ONE_SIM_VARIANTS >= variants_count.exp) {
 			done = true;
 		}
 
@@ -115,7 +117,7 @@ namespace evolution {
 			unsigned i = 0;
 			for (auto output: this->individuals[index].repres->chromosome->wire_out) {
 				xor_outputs[i].vec = test_circuic[output.first].vec ^ reference_circuic[this->reference_inverse_wire_out[output.second]].vec;
-				total_error += simulation::bits_count(xor_outputs[i], variants_count) * config_parse->port_weight(output.second);
+				total_error += simulation::bits_count(xor_outputs[i], variants_count_sim) * config_parse->port_weight(output.second);
 				i++;
 			}
 
@@ -131,7 +133,7 @@ namespace evolution {
 			}
 
 			//Update inputs for next simulation
-			for (unsigned i = ONE_SIM_VARIANTS; i <= TO_REAL_INPUT(this->individuals[index].repres->chromosome->last_input); i++) {
+			for (unsigned i = ONE_SIM_VARIANTS; i < TO_REAL_INPUT(this->individuals[index].repres->chromosome->last_input + 1); i++) {
 				variant_counter[i] = (variant_counter[i] + 1) % (1 << (i - ONE_SIM_VARIANTS));
 
 				if (variant_counter[i] == 0) {
@@ -149,7 +151,7 @@ namespace evolution {
 			}
 		} while (!done);
 
-		this->individuals[index].mae = (float) total_error / variants_count;
+		this->individuals[index].mae = total_error / variants_count;
 
 		if (this->individuals[index].mae > this->max_abs_loss) {
 			this->individuals[index].score = INFINITY;

src/simulation.cpp

@@ -26,13 +26,13 @@ namespace simulation {
 		return count;
 	}
 
-	unsigned one_max_loss(std::vector<io_t> xor_outputs, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> rtl_ports, config::parse *config_parse) {
-		unsigned max = 0;
+	float one_max_loss(std::vector<io_t> xor_outputs, std::map<genome::io_id_t, Yosys::RTLIL::SigBit> rtl_ports, config::parse *config_parse) {
+		float max = 0;
 
 		for (unsigned byte = 0; byte < SIM_BYTES_COUNT; byte++) {
 			for (unsigned bit = 0; bit < 8; bit++) {
 				unsigned port_id = 0;
-				unsigned count   = 0;
+				float    count   = 0;
 				for (auto output: rtl_ports) {
 					count                          += (xor_outputs[port_id].byte[byte] & 1) * config_parse->port_weight(output.second);
 					xor_outputs[port_id].byte[byte] = xor_outputs[port_id].byte[byte] >> 1;

tests/128bparity-gates-cgp/code.v

@@ -0,0 +1,4 @@
+module paritydev (input [127:0] a,  
+                  output par);
+   assign par = ^a;  
+endmodule

tests/128bparity-gates-cgp/run

@@ -0,0 +1,6 @@
+read_verilog tests/128bparity-gates-cgp/code.v
+techmap
+opt
+abc
+cgploss -generations=3 -generation_size=3 -selection_size=1 -representation=gates
+write_verilog test_out.v

tests/128bparity-gates-cgp/tb.v

@@ -0,0 +1,33 @@
+module fulladder_tb;
+  task assert(input condition);
+    if(!condition)
+      $fatal;
+  endtask
+
+  reg  [127:0] a;
+  reg  par_exp;
+  wire par;
+
+  integer i;
+
+  paritydev UUT(
+    .a(a),
+    .par(par)
+  );
+
+  initial begin
+    a    <= 0;
+
+    for (i = 0; i < 131072; i = i + 1) begin
+      a    <= {$random, $random, $random, $random};
+
+      #10
+
+      par_exp = ^a; 
+
+      #10
+
+      assert(par === par_exp);
+    end
+  end
+endmodule