Logic-Circuits-Labs

Table of Contents

• Project Description
• IDE
• Installation
• Contributors

Project Description

For a detailed Labs description, please refer to the Labs Description PDF.

Lab03: Karnaugh table

The Pre Report for this Part is provided in the Lab03 Pre Report PDF.

Lab04: Introduction to Verilog

The Pre Report for this Part is provided in the Lab04 Pre Report PDF.
The Implemented Project is in Lab04 Project.

Lab05: Encoder, Decoder, Multiplexer

The Pre Report for this Part is provided in the Lab05 Pre Report PDF.
The Implemented Project is in Lab05 Project.

Lab06: Comparator

The Pre Report for this Part is provided in the Lab06 Pre Report PDF.
The Implemented Project is in Lab06 Project.

Lab07: Full Adder, Adder-Subtractor

The Pre Report for this Part is provided in the Lab07 Pre Report PDF.
The Implemented Project is in Lab07 Project.

Lab08:ALU

The Pre Report for this Part is provided in the Lab08 Pre Report PDF.
The Implemented Project is in Lab08 Project.

Lab09: Sequentioal logic units, Flip Flop

The Pre Report for this Part is provided in the Lab09 Pre Report PDF.
The Implemented Project is in Lab09 Project.

Lab10: FSM

The Pre Report for this Part is provided in the Lab10 Pre Report PDF.
The Implemented Project is in Lab10 Project.

IDE

This project is developed using Xilinx ISE Design Suite.

Installation

Step-by-step instructions on how to get the development environment running:

Steps

1. Clone repository to your local system.
2. Launch Xilinx ISE Design Suite.
3. Click on File > Open Project.
4. Navigate to the folder where you cloned the repository and select the .xise project file.
5. Click on Simulate Behavioral Model in the processes pane under Simulation.
6. Use the ISim tool to run simulations and view waveforms.
7. Configure inputs and observe outputs to validate the design.

Contributors

• Fatemeh Abdi