Merge pull request #2 from MattiaDif/dev

simulation script update

code/init_prj.tcl

@@ -3,16 +3,30 @@ set project_name "MyProject"
 set project_directory "D:/GitHub/Tcl-Vivado/pl_project/$project_name"
 set top_module "top_level"
 set target_device "XC7A100TCSG324-1"
+set language "VHDL"
+
+
+# Overwrite or not if a project with the same name is already present in the folder
+set force 1
 
 
 # Create the project and directory structure setting up the board of interest
 #create_project -force -part XC7A100TCSG324-1 D:/GitHub/Tcl-Vivado/pl_project
-create_project $project_name $project_directory -part $target_device
+if {$force} {
+    create_project -force $project_name $project_directory -part $target_device
+} else {
+    create_project $project_name $project_directory -part $target_device
+}
 
 
 # Add various sources (no copy) to the project: sources, testbenches, constraint/s files
-add_files {D:/GitHub/Tcl-Vivado/code/src/}                                                                
+# Add all file of the folder src/
+add_files {D:/GitHub/Tcl-Vivado/code/src/}  
+
+# Add all file of the folder sim/
 add_files -fileset sim_1 {D:/GitHub/Tcl-Vivado/code/sim/}
+
+# Add specific file
 add_files -fileset constrs_1 D:/GitHub/Tcl-Vivado/code/xdc/Arty-A7-100-Master.xdc
 
 
@@ -22,9 +36,9 @@ set_property top $top_module [current_fileset]
 
 # Set target language of current project, VHDL or Verilog 
 # Project language
-set_property target_language VHDL [current_project]
+set_property target_language $language [current_project]
 # Simulator language
-set_property simulator_language VHDL [current_project]
+set_property simulator_language $language [current_project]
 
 
 

code/sim/adder_tb.vhd

@@ -11,23 +11,20 @@ architecture Behavioral of adder_tb is
         port (
             a     : in  std_logic_vector(3 downto 0);
             b     : in  std_logic_vector(3 downto 0);
-            sum   : out std_logic_vector(3 downto 0);
-            carry : out std_logic
+            sum   : out std_logic_vector(3 downto 0)
         );
     end component;
 
     -- Signal declarations
     signal a     : std_logic_vector(3 downto 0);
     signal b     : std_logic_vector(3 downto 0);
     signal sum   : std_logic_vector(3 downto 0);
-    signal carry : std_logic;
 begin
     -- Instantiate the Adder
     UUT: adder port map (
         a => a,
         b => b,
-        sum => sum,
-        carry => carry
+        sum => sum
     );
 
     -- Test process

code/sim_prj.tcl

@@ -0,0 +1,15 @@
+# Define project variables
+set selected_simulator XSim
+set top_module_sim "adder_tb"
+
+
+# Set module to simulate
+set_property top $top_module_sim [get_filesets sim_1]
+
+#Set target simulator
+set_property target_simulator $selected_simulator [current_project]
+
+# Lunch simulation
+launch_simulation
+
+puts "Simulation launched with $selected_simulator."

code/src/adder.vhd

@@ -6,24 +6,19 @@ entity adder is
     port (
         a     : in  std_logic_vector(3 downto 0);  -- 4-bit input A
         b     : in  std_logic_vector(3 downto 0);  -- 4-bit input B
-        sum   : out std_logic_vector(3 downto 0);  -- 4-bit output sum
-        carry : out std_logic                     -- carry-out
+        sum   : out std_logic_vector(3 downto 0)   -- 4-bit output sum
     );
 end entity adder;
 
 
 architecture Behavioral of adder is
+
+    signal tmp_sum : unsigned(3 downto 0);
+
 begin
-    process(a, b)
-        variable tmp_sum : unsigned(4 downto 0);  -- Temporary variable to hold the sum with carry
-    begin
-        -- Perform the addition
-        tmp_sum := unsigned(a) + unsigned(b);
-
-        -- Assign the result to the output ports
-        sum <= std_logic_vector(tmp_sum(3 downto 0));  -- Lower 4 bits for the sum
-        carry <= tmp_sum(4);                           -- 5th bit for the carry
-    end process;
 
+        tmp_sum <= unsigned(a) + unsigned(b);
+        -- Assign the result to the output ports
+        sum <= std_logic_vector(tmp_sum);  -- Lower 4 bits for the sum
 
 end architecture Behavioral;