👋 Hi, I am Kaushal Kumar Kumawat, a dedicated and proficient Electronics and Engineering Physics graduate who has completed a Master's degree at the National Institute of Technology, Warangal. With a robust academic background and hands-on experience in FPGA development and data acquisition architectures, I excel in designing and implementing innovative solutions for complex engineering challenges.

I have extensive experience in FPGA development and data acquisition architectures. Currently, I am an FPGA Developer at Vicharak Computers PVT LTD, where I design architectures that generate multiple peripherals on FPGA and implement various data communication protocols. Previously, as an FPGA Intern at GalaxEye Space LTD, I designed a data acquisition architecture for CMOS sensors using LVDS serial communication protocols. Additionally, I have worked on various academic projects at the National Institute of Technology Warangal, including RTL Design, combinational and sequential circuits, and MATLAB-based image and signal processing.

🔭 Currently working on: Single Board Computer for Parallel Reconfigurable Hardware Development

🌱 Learning: Advanced digital design techniques and SoC integration

💬 Ask me about: Verilog, SystemVerilog, and FPGA-based system design

⚡ Fun fact: I enjoy solving complex problems and am always eager to learn new technologies!

FPGA Developer (Feb 2024 - Present) | Surat, Gujarat

Created a comprehensive FPGA peripheral library, facilitating easy integration of multiple communication proto- cols and control interfaces, called Periplex.

Successfully integrated various peripherals, including UART, I2C, SPI, GPIO, PWM, WS2812, and CAN, into the Periplex system.

Configured and optimized peripheral modules for specific application requirements in a modular, scalable design. Developed robust communication solutions for real-time systems, with flexible configuration options for various peripheral devices.

FPGA Intern (June 2023 - July 2023) | Bengaluru

Designed a data acquisition architecture for CMOS Sensor interfaced by LVDS serial communication protocol with System on Chip (SoC). Utilized Xilinx Vivado 2023.1 for Zynq 7000 SoC Embedded Dev Board for frame acquisition and preprocessing.

Programming Languages: C/C++

Hardware Description/Verification Languages: Verilog HDL

Communication Protocols: UART, I2C, SPI, GPIO, PWM, WS2812, CAN, AMBA APB

Developer Tools: Xilinx Vivado-Vitis, VS Code, Multisim, MATLAB, Keil, Efinix Efinity, iVerilog, GTKWave

Hands-on Experience: Zynq 7000 SoC, FPGA Artix-7, 8086 Microprocessor, 8051 and ARM-7 Microcontroller, Arduino UNO R3, Trion T120 FPGA

Soft Skills: Time Management, Quick Learner, Problem Solving, Logical Thinking, Teamwork, Documentation