ALU.vcd

$date
	Wed Nov 22 13:41:12 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module ALU_tb $end
$var wire 1 ! Zero $end
$var wire 32 " Result [31:0] $end
$var wire 1 # OverFlow $end
$var wire 1 $ Negative $end
$var wire 1 % Carry $end
$var reg 32 & A [31:0] $end
$var reg 4 ' ALUControl [3:0] $end
$var reg 32 ( Accumulator [31:0] $end
$var reg 32 ) B [31:0] $end
$scope module uut $end
$var wire 32 * A [31:0] $end
$var wire 4 + ALUControl [3:0] $end
$var wire 32 , Accumulator [31:0] $end
$var wire 32 - B [31:0] $end
$var wire 32 . Sum [31:0] $end
$var wire 64 / MultResult [63:0] $end
$var reg 1 % Carry $end
$var reg 1 $ Negative $end
$var reg 1 # OverFlow $end
$var reg 32 0 Result [31:0] $end
$var reg 1 ! Zero $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
b11001 0
b10010110 /
b11001 .
b1010 -
b0 ,
b0 +
b1111 *
b1010 )
b0 (
b0 '
b1111 &
0%
0$
0#
b11001 "
0!
$end
#10000
b101 "
b101 0
b101 .
b1 '
b1 +
b1111 )
b1111 -
b100101100 /
b10100 &
b10100 *
#20000
b11111111111111111111111111111111 .
1!
b0 "
b0 0
b10 '
b10 +
b1010101010101010101010101010101 )
b1010101010101010101010101010101 -
b11100011100011100011100011100001110001110001110001110001110010 /
b10101010101010101010101010101010 &
b10101010101010101010101010101010 *
#30000
b1010101010101010101010101010101 .
1$
0!
b11111111111111111111111111111111 "
b11111111111111111111111111111111 0
b11 '
b11 +
#40000
b1000 .
0$
b10110 "
b10110 0
b100 '
b100 +
b111 (
b111 ,
b11 )
b11 -
b1111 /
b101 &
b101 *
#50000