32bit-RISC-V-Processor

this is a verilog code for 32 bit RISC V processor ALU for basic arithmetic and logical operations

Implementation:

GDS Layout:

Tool Used VS Code: Verilog

GTKwave: Capture Input & output signal Waveform

Qflow: RTL to GDS

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
Gate_level_netlist		Gate_level_netlist
ALU.v		ALU.v
ALU.vcd		ALU.vcd
ALU_Decoder.v		ALU_Decoder.v
ALU_tb.v		ALU_tb.v
ALU_tb.vvp		ALU_tb.vvp
Control_Unit_Top.v		Control_Unit_Top.v
Data_Memory.v		Data_Memory.v
Instruction_Memory.v		Instruction_Memory.v
Main_Decoder.v		Main_Decoder.v
Mux.v		Mux.v
Mux_tb.v		Mux_tb.v
PC.v		PC.v
PC_Adder.v		PC_Adder.v
PC_Module_tb.v		PC_Module_tb.v
README.md		README.md
Register_File.v		Register_File.v
Register_File_tb.v		Register_File_tb.v
Sign_Extend.v		Sign_Extend.v
Single Cycle.vcd		Single Cycle.vcd
Single_Cycle_Top.v		Single_Cycle_Top.v
Single_Cycle_Top.vvp		Single_Cycle_Top.vvp
Single_Cycle_Top_Tb.v		Single_Cycle_Top_Tb.v
generate_test_bench.py		generate_test_bench.py
memfile.hex		memfile.hex

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