Single Cycle.vcd

$date
	Fri Oct 27 11:06:06 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module Single_Cycle_Top_Tb $end
$var reg 1 ! clk $end
$var reg 1 " rst $end
$scope module Single_Cycle_Top $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 32 # SrcB [31:0] $end
$var wire 1 $ ResultSrc $end
$var wire 32 % Result [31:0] $end
$var wire 1 & RegWrite $end
$var wire 32 ' ReadData [31:0] $end
$var wire 32 ( RD_Instr [31:0] $end
$var wire 32 ) RD2_Top [31:0] $end
$var wire 32 * RD1_Top [31:0] $end
$var wire 32 + PC_Top [31:0] $end
$var wire 32 , PCPlus4 [31:0] $end
$var wire 1 - MemWrite $end
$var wire 32 . Imm_Ext_Top [31:0] $end
$var wire 2 / ImmSrc [1:0] $end
$var wire 1 0 ALUSrc $end
$var wire 32 1 ALUResult [31:0] $end
$var wire 3 2 ALUControl_Top [2:0] $end
$scope module ALU $end
$var wire 1 3 Carry $end
$var wire 1 4 OverFlow $end
$var wire 1 5 Zero $end
$var wire 32 6 Sum [31:0] $end
$var wire 32 7 Result [31:0] $end
$var wire 1 8 Negative $end
$var wire 1 9 Cout $end
$var wire 32 : B [31:0] $end
$var wire 3 ; ALUControl [2:0] $end
$var wire 32 < A [31:0] $end
$upscope $end
$scope module Control_Unit_Top $end
$var wire 7 = Op [6:0] $end
$var wire 3 > funct3 [2:0] $end
$var wire 7 ? funct7 [6:0] $end
$var wire 1 $ ResultSrc $end
$var wire 1 & RegWrite $end
$var wire 1 - MemWrite $end
$var wire 2 @ ImmSrc [1:0] $end
$var wire 1 A Branch $end
$var wire 1 0 ALUSrc $end
$var wire 2 B ALUOp [1:0] $end
$var wire 3 C ALUControl [2:0] $end
$scope module ALU_Decoder $end
$var wire 3 D funct3 [2:0] $end
$var wire 7 E funct7 [6:0] $end
$var wire 7 F op [6:0] $end
$var wire 2 G ALUOp [1:0] $end
$var wire 3 H ALUControl [2:0] $end
$upscope $end
$scope module Main_Decoder $end
$var wire 7 I Op [6:0] $end
$var wire 1 $ ResultSrc $end
$var wire 1 & RegWrite $end
$var wire 1 - MemWrite $end
$var wire 2 J ImmSrc [1:0] $end
$var wire 1 A Branch $end
$var wire 1 0 ALUSrc $end
$var wire 2 K ALUOp [1:0] $end
$upscope $end
$upscope $end
$scope module Data_Memory $end
$var wire 32 L A [31:0] $end
$var wire 1 - WE $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 32 M WD [31:0] $end
$var wire 32 N RD [31:0] $end
$upscope $end
$scope module Instruction_Memory $end
$var wire 1 " rst $end
$var wire 32 O RD [31:0] $end
$var wire 32 P A [31:0] $end
$upscope $end
$scope module Mux_DataMemory_to_Register $end
$var wire 32 Q a [31:0] $end
$var wire 32 R b [31:0] $end
$var wire 1 $ s $end
$var wire 32 S c [31:0] $end
$upscope $end
$scope module Mux_Register_to_ALU $end
$var wire 1 0 s $end
$var wire 32 T c [31:0] $end
$var wire 32 U b [31:0] $end
$var wire 32 V a [31:0] $end
$upscope $end
$scope module PC $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 32 W PC_Next [31:0] $end
$var reg 32 X PC [31:0] $end
$upscope $end
$scope module PC_Adder $end
$var wire 32 Y a [31:0] $end
$var wire 32 Z b [31:0] $end
$var wire 32 [ c [31:0] $end
$upscope $end
$scope module Register_File $end
$var wire 5 \ A1 [4:0] $end
$var wire 5 ] A2 [4:0] $end
$var wire 5 ^ A3 [4:0] $end
$var wire 32 _ WD3 [31:0] $end
$var wire 1 & WE3 $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 32 ` RD2 [31:0] $end
$var wire 32 a RD1 [31:0] $end
$upscope $end
$scope module Sign_Extend $end
$var wire 1 b ImmSrc $end
$var wire 32 c In [31:0] $end
$var wire 32 d Imm_Ext [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
b0 d
b0 c
0b
b0 a
b0 `
b0 _
b0 ^
b0 ]
b0 \
bx [
b100 Z
bx Y
bx X
bx W
b0 V
b0 U
b0 T
b0 S
b0 R
b0 Q
bx P
b0 O
b0 N
b0 M
b0 L
b0 K
b0 J
b0 I
b0 H
b0 G
b0 F
b0 E
b0 D
b0 C
b0 B
0A
b0 @
b0 ?
b0 >
b0 =
b0 <
b0 ;
b0 :
09
08
b0 7
b0 6
15
04
03
b0 2
b0 1
00
b0 /
b0 .
0-
bx ,
bx +
b0 *
b0 )
b0 (
b0 '
0&
b0 %
0$
b0 #
0"
0!
$end
#50
b100 ,
b100 W
b100 [
b0 +
b0 P
b0 X
b0 Y
1!
#100
0!
#150
b11 2
b11 ;
b11 C
b11 H
04
08
b101 %
b101 S
b101 _
05
1&
b101 1
b101 7
b101 L
b101 Q
b110 .
b110 U
b110 d
b10 B
b10 G
b10 K
b110011 ?
b110011 E
b110 >
b110 D
b110011 =
b110011 F
b110011 I
b1 ^
b110 ]
b101 \
b1 6
b100 #
b100 :
b100 T
bx '
bx N
bx R
b11000101110000010110011 (
b11000101110000010110011 O
b11000101110000010110011 c
b101 *
b101 <
b101 a
b100 )
b100 M
b100 V
b100 `
1"
1!
#200
0!
#250
b100 %
b100 S
b100 _
b100 1
b100 7
b100 L
b100 Q
b1001 6
b10 2
b10 ;
b10 C
b10 H
b111 >
b111 D
b11110 ^
b11000101111111100110011 (
b11000101111111100110011 O
b11000101111111100110011 c
b1000 ,
b1000 W
b1000 [
b100 +
b100 P
b100 X
b100 Y
1!
#300
0!
#350
x8
x5
x4
bx 1
bx 7
bx L
bx Q
bx %
bx S
bx _
x&
xb
x0
bx 2
bx ;
bx C
bx H
bx #
bx :
bx T
bx 6
bx .
bx U
bx d
bx /
bx @
bx J
x-
x$
xA
bx B
bx G
bx K
bx )
bx M
bx V
bx `
bx *
bx <
bx a
bx ?
bx E
bx >
bx D
bx =
bx F
bx I
bx ^
bx ]
bx \
bx (
bx O
bx c
b1100 ,
b1100 W
b1100 [
b1000 +
b1000 P
b1000 X
b1000 Y
1!
#400
0!
#450
b10000 ,
b10000 W
b10000 [
b1100 +
b1100 P
b1100 X
b1100 Y
1!
#500
0!
#550
b10100 ,
b10100 W
b10100 [
b10000 +
b10000 P
b10000 X
b10000 Y
1!
#600
0!