references.bib

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	author        = "Tetsutaro Hashimoto and others",
	title         = "{An Adaptive-Clocking-Control Circuit with 7.5\% Frequency Gain for SPARC Processors}",
	journal       = "IEEE J. Solid-State Circuits",
	volume        = "53",
	number        = "4",
	pages         = "1028-1037",
	year          = "Aug. 2018"
}

@article{wilcox2015,
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	author        = "Kathryn Wilcox and others",
	title         = "{Steamroller Module and Adaptive Clocking System in 28 nm CMOS}",
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}

@article{ahmad2017,
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	title         = "{A 0.5-9.5-GHz, 1.2-$\mu$s Lock-Time Fractional-N DPLL with $\pm$1.25\%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling}",
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}

@inproceedings{floyd2017,
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}

@article{bowman2016,
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	author        = "Keith A. Bowman and others",
	title         = "{A 16nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range}",
	journal       = "IEEE J. Solid-State Circuits",
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}

@article{kurd2009,
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	author		= "Nasser Kurd and others",
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}

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@article{kwak2016self,
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@article{wong2006enhancing,
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}