Customising the layout by including a custom made inverter cell (sky130_vsdinv) into our layout.

PHYSICAL DESIGN

This repository contains all the information needed to build and run openlane flow, which has the capability to perform full ASIC implementation steps from RTL to GDSII. In addition, it also contains procedures on how to create a custom LEF file and plugging it into an openlane flow

Introduction to OpenLane flow

OpenLane is a completely automated RTL to GDSII flow which embeds in it different opensource tools, namely, OpenROAD, Yosys, ABC,etc., apart from many custom methodology scripts for design exploration and optimization. Openlane is built around Skywater 130nm process node and is capable of performing full ASIC implementation steps from RTL all the way down to GDSII. The flow-chart below gives a better picture of openlane flow as a whole

Overview Of Physical Design Flow

Place and Route(PnR) is the core of any ASIC implemantation and OpenLane flow integrates into it several key opensource tools which perform each of the respective stages of PnR. Below are the stages and respective tools that are called by OpenLane

Synthesis
- Genetaring gate level netlist(Yosys)
- cell mapping (abc)
- Performing Pre-layout STA(OpenSTA)
Floorplanning
- Defining the core are for the macro as well as the cell sites and tracks (init_fp).
- Placing the macro input and output ports (io_placer).
- Generating the power distribution network (pdn).
Placement
- Global placement (RePLace).
- Detailed Placement : To legalise the globally placed components (OpenDP).
Cts
- Synthesising the clock tree (Triton CTS).
Routing
- Global Routing to generate a guide file for detailed router (FastRoute).
- Detailed Routing (TritonRoute).
GDSII Generation
- Streaming out the final GDSII layout file from the routed def (Magic).

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

More about OpenLane at https://github.com/The-OpenROAD-Project/OpenLane

Installation Instructions

apt install -y build-essential python3 python3-venv python3-pip

Docker installation process https://docs.docker.com/engine/install/ubuntu

Follow these commands after moving to the home directory

$ git clone https://github.com/The-OPENROAD-Project/OpenLane.git
$ cd OpenLane
$ make
$ make test

Magic

Magic is a VLSI layout tool, widely cited as being the easiest tool to use for circuit layout.

More about Magic at https://opencircuitdesign.com/magic/index.html

Before installing Magic run the following commands to fulfill system requirements

$   sudo apt-get install m4
$   sudo apt-get install tcsh
$   sudo apt-get install csh
$   sudo apt-get install libx11-dev
$   sudo apt-get install tcl-dev tk-dev
$   sudo apt-get install libcairo2-dev
$   sudo apt-get install mesa-common-dev libglu1-mesa-dev
$   sudo apt-get install libncurses-dev

To install Magic go to home directory

$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic
$ ./configure
$ make
$ make install

type Magic in the terminal to check whether it is installed or not.

Customising the layout by including a custom made inverter cell (sky130_vsdinv) into our layout.

Introduction to LEF file

For a PnR tool to correctly place and route a block (a macro or a std. cell), it doesn't need to know entire layout information of the block; just the pin positions, PR boundary is sufficient. These minimal and abstracted information is provided to the tool by the Library Exchange Format (LEF) file. LEF file also serves the purpose of protecting intellectual property and is basically of two types:

Cell LEF : Gives the positions of pins, PR boundary and metal layer information

Tech LEF : information about available metal layer, via information, DRCs of particular technology used by placer and route

Creating SKY130_vsdinv cell lef file
- First get the git repository vsdstdcelldesign. Type the following command to get the repository.
  
  git clone https://github.com/nickson-jose/vsdstdcelldesign.git
  
  This creates a vsdstdcelldesign named folder in the openlane directory. To invoke magic to view the sky130_inv.mag file, the sky130A.tech file must be included in the command along with its path. To ease up the complexity of this command, the tech file can be copied from the magic folder to the vsdstdcelldesign folder.
  
  The sky130_inv.mag file can then be invoked in Magic using
  
  magic -T sky130A.tech sky130_inv.mag &
  
  LEF or library exchange format: A format that tells us about cell boundaries, VDD and GND lines. It contains no info about the logic of circuit and is also used to protect the IP.
  
  SPICE extraction: Within the Magic environment, following commands are used in tkcon to achieve .mag to .spice extraction:
```
extract all
ext2spice cthresh 0 rethresh 0
ext2spice
```
  The next step is setting port class and port use attributes. The "class" and "use" properties of the port have no internal meaning to magic but are used by the LEF and DEF format read and write routines, and match the LEF/DEF CLASS and USE properties for macro cell pins. These attributes are set in tkcon window (after selecting each port on layout window. A keyboard shortcut would be,repeatedly pressing s till that port gets highlighed).
  
  The tkcon command window of the port classification is shown in the image below:
  
  In the next step, use lef write command to write the LEF file with the same nomenclature as that of the layout .mag file. This will create a sky130_vsdinv.lef file in the same folder.
Including the SKY130_vsdinv cell in the design

Copy the lib files and the created sky130_vsdinv.lef file to your design src directory.

Modify the config.json file by including the following lines.

"LIB_SYNTH":"dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST":"dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST":"dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL":"dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB":"dir::src/*",
"SYNTH_DRIVING_CELL":"sky130_vsdinv"

Intialising OpenLane and Running Synthesis

1.We run the OpenLane in the interactive mode to include our custom made lef file(SKY130_vsdinv.lef) before synthesis, so that the openlane recognises our lef files during the flow for mapping.

Commands to run the openlane in interactive mode

cd OpenLane
make mount
./flow.tcl -interactive

2.Preparing the design and including the lef files:

prep -design picorv32a
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs

3.Synthesis: run_synthesis yosys translates RTL into circuit with generic components and abc maps the circuit to standard cells.

The synthesized Netlist is present in the results folder and the stats are present in the log folder.

slack report with the custom cell

4.Floorplan: run_floorplan

Post the floorplan, a .def file is created in the results folder. We can review the code for floorplan in the floorplan.tcl file present in the scripts/tcl_commands folder. All the switches with which we can ammend the floorplan process can be found in floorplan.tcl file present in the configuration/floorplan.tcl folder.

To view the floorplan use the magic tool with the following command.

magic -T /home/pa1mantri/.volare/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read picorv32.def

Die-Area post Floorplan

All the standard cells are found at the corner of the chip, whcih will be placed at the placement stage. PDN(power distribution network) also happens at this stage with rails,straps and rings in the chip.

5.Placement: The synthesized netlist is to be placed on the floorplan. Placement happens in two steps

Global Placement: It finds optimal position for all cells which may not be legal and cells may overlap. Optimization is done through reduction of half parameter wire length.

Detailed Placement: It alters the position of cells post global placement so as to legalise them.

After the placement, the results can be viewed on magic within Results/placement directory with the following command

magic -T /home/pa1mantri/.volare/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read picorv32.def

SKY130_vsdinv cell post placement

after using expand command in the tkcon window:

Area post Placement

resizing_sta report post placement

slack report post placement

6.Clock Tree Synthesis

The purpose of building a clock tree is enable the clock input to reach every element and to ensure a zero clock skew. H-tree is a common methodology followed in CTS. Before attempting a CTS run in TritonCTS tool, if the slack was attempted to be reduced in previous run, the netlist may have gotten modified by cell replacement techniques. Therefore, the verilog file needs to be modified using the write_verilog command. Then, the synthesis, floorplan and placement is run again. To run the cts c command is run_cts

slack report post CTS

Power report post CTS

Skew Report post CTS

Sta report post cts

7.Routing: There are two stages of Routing 1.Global Routing : Routing region is divided into rectangle grids which are represented as course 3D routes (Fastroute tool). 2.Detailed Routing : Finer grids and routing guides used to implement physical wiring (TritonRoute tool).