Tested and verified in-system

cdc/obi_cdc_fast_primary.v

@@ -10,6 +10,8 @@
 //              clock domain is as fast or faster than the secondary device's
 //              clock domain.
 //
+// SPDX-License-Identifier: Apache-2.0
+//
 ///////////////////////////////////////////////////////////////////////////////
 
 module obi_cdc_fast_primary (
@@ -59,16 +61,18 @@ module obi_cdc_fast_primary (
        this way, so the warning is inappropriate. */
 
     always @(posedge secondary_clk_i) begin
-        if ((gnt_ack_ff3 && !gnt_ack_ff2) || !rst_n_secondary_ff2)
+        if ((gnt_ack_ff2 && !gnt_ack_ff3) || !rst_n_secondary_ff2)
             gnt_in_flight <= 'b0;
         else if (req_ff2 && secondary_gnt_i && !gnt_in_flight)
             gnt_in_flight <= 'b1;
     end
 
     always @(posedge ctrl_clk_i or negedge gnt_in_flight) begin
-        if(!rst_n_ctrl_ff2 || !gnt_in_flight)
+        if(!gnt_in_flight)
+            gnt_ack <= 'b0;
+        else if(!rst_n_ctrl_ff2)
             gnt_ack <= 'b0;
-        else if(gnt_ff3 && !gnt_ff2)
+        else if(gnt_ff2 && !gnt_ff3)
             gnt_ack <= 'b1;
     end
 
@@ -110,8 +114,15 @@ module obi_cdc_fast_primary (
     // Primary bus outputs //
     /////////////////////////
 
-    assign ctrl_rdata_o = secondary_rdata_i;
-    assign ctrl_gnt_o = gnt_ff3 && !gnt_ff2;
+    assign ctrl_gnt_o = gnt_ff2 && !gnt_ff3;
+
+    always @(posedge ctrl_rvalid_o) begin
+        if (!rst_n_ctrl_ff2) begin
+            ctrl_rdata_o <= 32'hDEAD_BEEF;
+        end else begin
+            ctrl_rdata_o <= secondary_rdata_i;
+        end
+    end
 
     always @(posedge ctrl_clk_i) begin
         if (!rst_n_ctrl_ff2) begin

wishbone/wb_to_obi.v

@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`timescale 1ns / 1ps
 ///////////////////////////////////////////////////////////////////////////////
 //
 // Module Name: wb_to_obi
@@ -14,11 +14,14 @@
 //              provided. Any clock domain crossings must be handled by the 
 //              user.
 //
+// SPDX-License-Identifier: Apache-2.0
+//
 ///////////////////////////////////////////////////////////////////////////////
 
+
 module wb_to_obi (
     input               clk_i,
-    // Wishbone bus from master
+    // WishBone Master Ports
     input               wb_rst_i,  // Active high!
     input               wbs_stb_i,
     input               wbs_cyc_i, // Not Used in OBI
@@ -29,19 +32,18 @@ module wb_to_obi (
     output wire         wbs_ack_o,
     output wire  [31:0] wbs_dat_o,
 
-    // OBI Port to Slave
-    output wire         req_o,    
-    input               gnt_i,   
-    output wire  [31:0] addr_o,    
-    output wire         we_o,       
-    output wire  [3:0]  be_o,     
-    output wire  [31:0] wdata_o,  
-    input               rvalid_i,
-    input [31:0]        rdata_i   
+    // OBI Slave Ports
+    output wire         req_o,   
+    input               gnt_i,    
+    output wire  [31:0] addr_o,   
+    output wire         we_o,      
+    output wire  [3:0]  be_o,    
+    output wire  [31:0] wdata_o, 
+    input               rvalid_i, 
+    input [31:0]        rdata_i  
     );
 
-    reg read_outstanding, write_completed; 
-    wire read_accepted_a, write_accepted_a;
+    logic read_outstanding, write_completed, read_accepted_a, write_accepted_a;
     assign read_accepted_a  = (req_o && gnt_i) && !wbs_we_i;
     assign write_accepted_a = (req_o && gnt_i) && wbs_we_i;
 
@@ -53,7 +55,7 @@ module wb_to_obi (
             if (read_outstanding && (rvalid_i && !read_accepted_a))
                 read_outstanding <= 'b0;
             if (!read_outstanding && read_accepted_a)
-                read_outstanding <= 'b0;
+                read_outstanding <= 'b1;
         end
     end
 
@@ -63,7 +65,7 @@ module wb_to_obi (
     end
 
     // Address Signals
-    assign req_o     = wbs_stb_i;
+    assign req_o     = wbs_stb_i && !read_outstanding;
     assign addr_o    = wbs_adr_i;
     assign we_o      = wbs_we_i;
     assign be_o      = wbs_sel_i;