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fixed pad and pad array, added to library
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joaquin committed Jan 28, 2020
1 parent 343f49f commit 614870a
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Showing 8 changed files with 25 additions and 35 deletions.
10 changes: 9 additions & 1 deletion pp/components/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,11 @@
from pp.components.delay_snake import delay_snake
from pp.components.spiral_inner_io import spiral_inner_io_euler

# electrical test structures
# electrical
from pp.components.electrical.pad import pad
from pp.components.electrical.pad import pad_array

# electrical PCM
from pp.components.pcm.test_resistance import test_resistance
from pp.components.pcm.test_via import test_via

Expand Down Expand Up @@ -101,6 +105,8 @@
"mmi2x2": mmi2x2,
"mzi2x2": mzi2x2,
"mzi1x2": mzi1x2,
"pad": pad,
"pad_array": pad_array,
"rectangle": rectangle,
"ring": ring,
"ring_single_bus": ring_single_bus,
Expand Down Expand Up @@ -165,6 +171,8 @@ def component_factory(component_type, **settings):
"mmi1x2",
"mmi2x2",
"mzi_arm",
"pad",
"pad_array",
"rectangle",
"rectangle_centered",
"ring_single_bus",
Expand Down
27 changes: 7 additions & 20 deletions pp/components/electrical/pad.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,27 +20,14 @@ def pad(width=100.0, height=100.0, layer=LAYER.M3):

@autoname
def pad_array(pad=pad, start=(0, 0), spacing=(150, 0), n=6, port_list=["N"]):
""" column array of rectangular pads
""" array of rectangular pads
"""
start = (start[0] - n * spacing[0] / 2, start[1])
c = pp.Component()
pad = pp.call_if_func(pad)
parray = c.add_array(device=pad, start=start, spacing=spacing, num_devices=n)
for port_name in port_list:
for i, p in enumerate(parray):
port_name_new = "{}{}".format(port_name, i)
c.add_port(port=p.ports[port_name], name=port_name_new)
return c


@autoname
def pad_array_xcentered(pad=pad, start=(0, 0), spacing=(150, 0), n=6, port_list=["N"]):
start = (start[0] - n * spacing[0] / 2, start[1])
c = pp.Component()
pad = pp.call_if_func(pad)
parray = c.add_array(device=pad, start=start, spacing=spacing, num_devices=n)
for port_name in port_list:
for i, p in enumerate(parray):
for i in range(n):
p = c << pp.call_if_func(pad)
p.x = i * spacing[0]
for port_name in port_list:
port_name_new = "{}{}".format(port_name, i)
c.add_port(port=p.ports[port_name], name=port_name_new)
return c
Expand All @@ -49,7 +36,7 @@ def pad_array_xcentered(pad=pad, start=(0, 0), spacing=(150, 0), n=6, port_list=
if __name__ == "__main__":
# c = pad()
# c = pad(width=10, height=10)
c = pad_array_xcentered(n=2)
print(c.ports.keys())
# print(c.ports.keys())
# print(c.settings['spacing'])
c = pad_array()
pp.show(c)
2 changes: 1 addition & 1 deletion pp/components/grating_coupler/uniform_optimized.py
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
import pathlib
import numpy as np
from pp.component import Component
import pp

import pathlib

data_path = pathlib.Path(__file__).parent / "csv_data"

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11 changes: 2 additions & 9 deletions pp/components/pcm/cd_bend.py
Original file line number Diff line number Diff line change
Expand Up @@ -100,12 +100,5 @@ def wg(*a, **k):


if __name__ == "__main__":
pass
# c = pcm_bend_slot(
# width=[0.46, 0.5, 0.54, 0.46, 0.5, 0.54, 0.46, 0.5, 0.54],
# gap=[0.2, 0.2, 0.2, 0.225, 0.225, 0.225, 0.25, 0.25, 0.25],
# )
# c = pcm_bend_strip(width=[0.46, 0.5, 0.54])
# c = pcm_bend_rib(width=[0.46, 0.5, 0.54])
# c = cd_bend()
# c = cd_bend_slot()
c = cd_bend_strip(width=0.46)
pp.show(c)
2 changes: 1 addition & 1 deletion pp/components/pcm/test_comb.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ def test_comb(
comb_gnd_layer=None,
overlap_pad_layer=None,
):
""" Superconducting heater device
""" Superconducting heater device from phidl.geometry
Args:
pad_size=(200, 200)
Expand Down
3 changes: 2 additions & 1 deletion pp/components/pcm/test_resistance.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,8 @@ def test_resistance(
gnd_layer=None,
):

""" Creates an efficient meander to test resistance
""" meander to test resistance
from phidl.geometry
Args:
pad_size: Size of the two matched impedance pads (microns)
Expand Down
1 change: 1 addition & 0 deletions pp/components/pcm/test_via.py
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ def test_via(
via_layer=3,
):
""" Via cutback to extract via resistance
from phidl.geometry
Args:
num_vias=100
Expand Down
4 changes: 2 additions & 2 deletions pp/tests/test_factory.py
Original file line number Diff line number Diff line change
Expand Up @@ -180,13 +180,13 @@ def compare_component_hash(


if __name__ == "__main__":
lock_components_with_changes()
# lock_component("grating_coupler_tree")
# compare_component_hash("grating_coupler_tree")
test_all_components()
# test_all_components()
# rebuild_library()
# lock_component("waveguide")
# compare_component_hash("waveguide")
# lock_component("ring_double_bus")
# compare_component_hash("ring_double_bus")
# lock_components_with_changes()
# print_components_with_changes()

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