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[X86] combineConcatVectorOps - only concatenate single-use subops
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We could maybe extend this by allowing the lowest subop to have multiple uses and extract the lowest subvector result of the concatenated op, but let's just get the fix in first.

Fixes llvm#67333
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@RKSimon @tru
RKSimon authored and tru committed Oct 10, 2023
1 parent 5a13ce2 commit 37b79e7
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Showing 6 changed files with 358 additions and 164 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -57239,7 +57239,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
// TODO - combineX86ShufflesRecursively should handle shuffle concatenation
// but it currently struggles with different vector widths.
if (llvm::all_of(Ops, [Op0](SDValue Op) {
return Op.getOpcode() == Op0.getOpcode();
return Op.getOpcode() == Op0.getOpcode() && Op.hasOneUse();
})) {
auto ConcatSubOperand = [&](EVT VT, ArrayRef<SDValue> SubOps, unsigned I) {
SmallVector<SDValue> Subs;
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190 changes: 190 additions & 0 deletions llvm/test/CodeGen/X86/pr67333.ll
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@@ -0,0 +1,190 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0

define void @SHA256_Compress_Generic(ptr noundef %ctx) #1 {
; CHECK-LABEL: SHA256_Compress_Generic:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movbel 0, %eax
; CHECK-NEXT: movbel 12(%rdi), %ecx
; CHECK-NEXT: vmovd %eax, %xmm0
; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,0,1,2,3,128,128,128,128,128,128,128,128]
; CHECK-NEXT: vpshufb %xmm1, %xmm0, %xmm2
; CHECK-NEXT: vpsrld $17, %xmm2, %xmm0
; CHECK-NEXT: vpslld $15, %xmm2, %xmm3
; CHECK-NEXT: vpor %xmm0, %xmm3, %xmm0
; CHECK-NEXT: vpsrld $19, %xmm2, %xmm3
; CHECK-NEXT: vpslld $13, %xmm2, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpxor %xmm3, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vmovd %ecx, %xmm3
; CHECK-NEXT: vpshufb %xmm1, %xmm3, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm1
; CHECK-NEXT: vpsrld $17, %xmm1, %xmm0
; CHECK-NEXT: vpslld $15, %xmm1, %xmm3
; CHECK-NEXT: vpor %xmm0, %xmm3, %xmm0
; CHECK-NEXT: vpsrld $19, %xmm1, %xmm3
; CHECK-NEXT: vpslld $13, %xmm1, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpxor %xmm3, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpsrld $17, %xmm0, %xmm3
; CHECK-NEXT: vpslld $15, %xmm0, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpsrld $19, %xmm0, %xmm4
; CHECK-NEXT: vpslld $13, %xmm0, %xmm5
; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
; CHECK-NEXT: vpsrld $10, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm0, %xmm3, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
; CHECK-NEXT: vpsrld $17, %xmm0, %xmm3
; CHECK-NEXT: vpslld $15, %xmm0, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpsrld $19, %xmm0, %xmm4
; CHECK-NEXT: vpslld $13, %xmm0, %xmm5
; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
; CHECK-NEXT: vpsrld $10, %xmm0, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
; CHECK-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2,3]
; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,0,2,3]
; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm2
; CHECK-NEXT: vpsrld $17, %xmm2, %xmm3
; CHECK-NEXT: vpslld $15, %xmm2, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpsrld $19, %xmm2, %xmm4
; CHECK-NEXT: vpslld $13, %xmm2, %xmm5
; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
; CHECK-NEXT: vpsrld $10, %xmm2, %xmm2
; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpsrlq $32, %xmm1, %xmm3
; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm1
; CHECK-NEXT: vpsrld $17, %xmm1, %xmm2
; CHECK-NEXT: vpslld $15, %xmm1, %xmm4
; CHECK-NEXT: vpor %xmm2, %xmm4, %xmm2
; CHECK-NEXT: vpsrld $19, %xmm1, %xmm4
; CHECK-NEXT: vpslld $13, %xmm1, %xmm5
; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm2
; CHECK-NEXT: vpsrld $10, %xmm1, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm2
; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpsrld $17, %xmm2, %xmm3
; CHECK-NEXT: vpslld $15, %xmm2, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpsrld $19, %xmm2, %xmm4
; CHECK-NEXT: vpslld $13, %xmm2, %xmm5
; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
; CHECK-NEXT: vpsrld $10, %xmm2, %xmm2
; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vpsrld $17, %xmm0, %xmm2
; CHECK-NEXT: vpslld $15, %xmm0, %xmm3
; CHECK-NEXT: vpor %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpsrld $19, %xmm0, %xmm3
; CHECK-NEXT: vpslld $13, %xmm0, %xmm4
; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2
; CHECK-NEXT: vpsrld $10, %xmm0, %xmm3
; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2
; CHECK-NEXT: vpsllq $32, %xmm1, %xmm3
; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; CHECK-NEXT: vmovdqu %ymm0, 132(%rdi)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
%0 = load i32, ptr null, align 4
%1 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %0) #3
%arrayidx14 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 3
%2 = load i32, ptr %arrayidx14, align 4
%3 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %2) #3
%4 = insertelement <2 x i32> zeroinitializer, i32 %1, i64 1
%5 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 15, i32 15>)
%6 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 13, i32 13>)
%7 = xor <2 x i32> %5, %6
%8 = lshr <2 x i32> %4, zeroinitializer
%9 = xor <2 x i32> %7, %8
%10 = insertelement <2 x i32> zeroinitializer, i32 %3, i64 0
%11 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %10, <2 x i32> <i32 1, i32 2>
%12 = add <2 x i32> %11, %9
%13 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 15, i32 15>)
%14 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 13, i32 13>)
%15 = xor <2 x i32> %13, %14
%16 = lshr <2 x i32> %12, zeroinitializer
%17 = xor <2 x i32> %15, %16
%18 = add <2 x i32> %4, %17
%19 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 15, i32 15>)
%20 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 13, i32 13>)
%21 = xor <2 x i32> %19, %20
%22 = lshr <2 x i32> %18, <i32 10, i32 10>
%23 = xor <2 x i32> %21, %22
%24 = add <2 x i32> %4, %23
%25 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 15, i32 15>)
%26 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 13, i32 13>)
%27 = xor <2 x i32> %25, %26
%28 = lshr <2 x i32> %24, <i32 10, i32 10>
%29 = xor <2 x i32> %27, %28
%30 = shufflevector <2 x i32> %4, <2 x i32> %12, <2 x i32> <i32 1, i32 2>
%31 = add <2 x i32> %30, %29
%32 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 15, i32 15>)
%33 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 13, i32 13>)
%34 = xor <2 x i32> %32, %33
%35 = lshr <2 x i32> %31, <i32 10, i32 10>
%36 = xor <2 x i32> %34, %35
%37 = shufflevector <2 x i32> %12, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 2>
%38 = add <2 x i32> %37, %36
%arrayidx918 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 33
store <2 x i32> %38, ptr %arrayidx918, align 4
%arrayidx1012 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 35
%39 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 15, i32 15>)
%40 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 13, i32 13>)
%41 = xor <2 x i32> %39, %40
%42 = lshr <2 x i32> %38, <i32 10, i32 10>
%43 = xor <2 x i32> %41, %42
%44 = add <2 x i32> %37, %43
store <2 x i32> zeroinitializer, ptr %arrayidx1012, align 4
%arrayidx1106 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 37
%45 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 15, i32 15>)
%46 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 13, i32 13>)
%47 = xor <2 x i32> %45, %46
%48 = lshr <2 x i32> %44, <i32 10, i32 10>
%49 = xor <2 x i32> %47, %48
%50 = lshr <2 x i32> %24, zeroinitializer
%51 = add <2 x i32> %50, %49
store <2 x i32> %51, ptr %arrayidx1106, align 4
%arrayidx1200 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 39
%52 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 15, i32 15>)
%53 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 13, i32 13>)
%54 = xor <2 x i32> %52, %53
%55 = lshr <2 x i32> %51, <i32 10, i32 10>
%56 = xor <2 x i32> %54, %55
%57 = shufflevector <2 x i32> %38, <2 x i32> zeroinitializer, <2 x i32> <i32 poison, i32 0>
%58 = insertelement <2 x i32> %57, i32 0, i64 0
%59 = add <2 x i32> %58, %56
store <2 x i32> %59, ptr %arrayidx1200, align 4
ret void

; uselistorder directives
uselistorder <2 x i32> %4, { 7, 0, 1, 6, 5, 4, 3, 2 }
uselistorder <2 x i32> %38, { 6, 5, 4, 3, 2, 1, 0 }
}

declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #2

; uselistorder directives
uselistorder ptr @llvm.fshl.v2i32, { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 }

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #1 = { nounwind sspstrong memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "probe-stack"="inline-asm" "stack-protector-buffer-size"="8" "target-cpu"="skylake" "target-features"="+adx,+aes,+avx,+avx2,+bmi,+bmi2,+clflushopt,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #3 = { nounwind memory(none) }
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/subvector-broadcast.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1768,8 +1768,8 @@ define void @PR51226() {
; X86-AVX2-LABEL: PR51226:
; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X86-AVX2-NEXT: vpslld $16, %xmm0, %xmm0
; X86-AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; X86-AVX2-NEXT: vpslld $16, %ymm0, %ymm0
; X86-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-AVX2-NEXT: vminps %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vmovups %ymm0, (%eax)
Expand All @@ -1779,8 +1779,8 @@ define void @PR51226() {
; X86-AVX512-LABEL: PR51226:
; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X86-AVX512-NEXT: vpslld $16, %xmm0, %xmm0
; X86-AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; X86-AVX512-NEXT: vpslld $16, %ymm0, %ymm0
; X86-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-AVX512-NEXT: vminps %ymm1, %ymm0, %ymm0
; X86-AVX512-NEXT: vmovups %ymm0, (%eax)
Expand All @@ -1801,8 +1801,8 @@ define void @PR51226() {
; X64-AVX2-LABEL: PR51226:
; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX2-NEXT: vpslld $16, %xmm0, %xmm0
; X64-AVX2-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; X64-AVX2-NEXT: vpslld $16, %ymm0, %ymm0
; X64-AVX2-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-AVX2-NEXT: vminps %ymm1, %ymm0, %ymm0
; X64-AVX2-NEXT: vmovups %ymm0, (%rax)
Expand All @@ -1812,8 +1812,8 @@ define void @PR51226() {
; X64-AVX512-LABEL: PR51226:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-AVX512-NEXT: vpslld $16, %xmm0, %xmm0
; X64-AVX512-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
; X64-AVX512-NEXT: vpslld $16, %ymm0, %ymm0
; X64-AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-AVX512-NEXT: vminps %ymm1, %ymm0, %ymm0
; X64-AVX512-NEXT: vmovups %ymm0, (%rax)
Expand Down
16 changes: 9 additions & 7 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -726,17 +726,19 @@ define void @store_i8_stride7_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp
; AVX512BW-SLOW-NEXT: vmovq {{.*#+}} xmm3 = mem[0],zero
; AVX512BW-SLOW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512BW-SLOW-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm3[0],ymm0[2],ymm3[2]
; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm1 = zmm0[0,2,1,3,4,6,5,7]
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm0[0,2,1,3]
; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm1 = zero,zero,zero,zero,zmm1[0,8],zero,zero,zero,zero,zero,zmm1[1,9],zero,zero,zero,zero,zero,zero,zero,zmm1[18],zero,zero,zero,zero,zero,zero,zmm1[19],zero,zero,zero,zero,zmm1[36,44],zero,zero,zero,zero,zero,zmm1[37,45],zero,zero,zero,zero,zero,zmm1[38,46,54],zero,zero,zero,zero,zero,zero,zmm1[55],zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[1,3,0,2,5,7,4,6]
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[1,3,0,2]
; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm0 = zero,zero,zero,zero,zero,zero,zmm0[0],zero,zero,zero,zero,zero,zero,zmm0[1],zero,zero,zero,zero,zmm0[18,26],zero,zero,zero,zero,zero,zmm0[19,27],zero,zero,zero,zero,zero,zero,zero,zmm0[36],zero,zero,zero,zero,zero,zero,zmm0[37],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zmm0[55,63],zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vporq %zmm1, %zmm0, %zmm0
; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm1
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm2 = zmm1[0,8],zero,zero,zero,zero,zero,zmm1[1,9],zero,zero,zero,zero,zero,zmm1[2,10,18,26],zero,zero,zero,zero,zero,zmm1[19,27],zero,zero,zero,zero,zero,zmm1[20,28],zero,zero,zero,zmm1[37,45],zero,zero,zero,zero,zero,zmm1[38,46],zero,zero,zero,zero,zero,zero,zero,zmm1[55,63],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} zmm1 = zmm1[2,3,0,1,6,7,4,5]
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm1 = zero,zero,zmm1[0,8],zero,zero,zero,zero,zero,zmm1[1,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zmm1[19,27],zero,zero,zero,zero,zero,zmm1[20,28],zero,zero,zero,zero,zero,zero,zero,zmm1[37,45],zero,zero,zero,zero,zero,zmm1[38,46],zero,zero,zero,zmm1[55,63],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vporq %zmm2, %zmm1, %zmm1
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm1 = zmm1[0,8],zero,zero,zero,zero,zero,zmm1[1,9],zero,zero,zero,zero,zero,zmm1[2,10,18,26],zero,zero,zero,zero,zero,zmm1[19,27],zero,zero,zero,zero,zero,zmm1[20,28],zero,zero,zero,zmm1[37,45],zero,zero,zero,zero,zero,zmm1[38,46],zero,zero,zero,zero,zero,zero,zero,zmm1[55,63],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm2[2,3,0,1]
; AVX512BW-SLOW-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm2
; AVX512BW-SLOW-NEXT: vpshufb {{.*#+}} zmm2 = zero,zero,zmm2[0,8],zero,zero,zero,zero,zero,zmm2[1,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zmm2[19,27],zero,zero,zero,zero,zero,zmm2[20,28],zero,zero,zero,zero,zero,zero,zero,zmm2[37,45],zero,zero,zero,zero,zero,zmm2[38,46],zero,zero,zero,zmm2[55,63],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512BW-SLOW-NEXT: vporq %zmm1, %zmm2, %zmm1
; AVX512BW-SLOW-NEXT: movabsq $63546854584629360, %rcx # imm = 0xE1C3870E1C3870
; AVX512BW-SLOW-NEXT: kmovq %rcx, %k1
; AVX512BW-SLOW-NEXT: vmovdqu8 %zmm0, %zmm1 {%k1}
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