[MLIR][OpenMP] Updated fix for intermixed TargetDataOp and TargetOp #56
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jsjodin
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skatrak,
agozillon,
DominikAdamski,
dpalermo and
TIFitis
jsjodin
commented
Mar 26, 2024
mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
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…n.cpp Remove extra newline
agozillon
approved these changes
Mar 26, 2024
skatrak
approved these changes
Mar 27, 2024
| @@ -3543,6 +3551,8 @@ convertTopLevelTargetOp(Operation *op, llvm::IRBuilderBase &builder, | |||
| LLVM::ModuleTranslation &moduleTranslation) { | |||
| if (isa<omp::TargetOp>(op)) | |||
| return convertOmpTarget(*op, builder, moduleTranslation); | |||
| if (isa<omp::TargetDataOp>(op)) | |||
| return convertOmpTargetData(op, builder, moduleTranslation); | |||
| bool interrupted = | |||
| op->walk<WalkOrder::PreOrder>([&](omp::TargetOp targetOp) { | |||
| if (failed(convertOmpTarget(*targetOp, builder, moduleTranslation))) | |||
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Wouldn't we need to find nested omp.target_data ops here as well?
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Yes, I forgot this wasn't a recursive function, so there should be a case for the TargetDataOp as well.
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| SmallVector<llvm::PHINode *> phis; | ||
| llvm::BasicBlock *continuationBlock = | ||
| convertOmpOpRegions(region, "omp.data.region", builder, | ||
| moduleTranslation, bodyGenStatus, &phis); | ||
| builder.SetInsertPoint(continuationBlock, | ||
| continuationBlock->getFirstInsertionPt()); |
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Just out of curiosity: Why did the original call break things? I see the only difference is that it does some special handling if there is a single block in the region.
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The special case assumes that that no new basic blocks are created, which does happen for omp.target, so it seems to generate code in the wrong place because of this.
dpalermo
approved these changes
Mar 28, 2024
searlmc1
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Aug 24, 2024
) Currently, process of replacing bitwise operations consisting of `LSR`/`LSL` with `And` is performed by `DAGCombiner`. However, in certain cases, the `AND` generated by this process can be removed. Consider following case: ``` lsr x8, x8, #56 and x8, x8, #0xfc ldr w0, [x2, x8] ret ``` In this case, we can remove the `AND` by changing the target of `LDR` to `[X2, X8, LSL #2]` and right-shifting amount change to 56 to 58. after changed: ``` lsr x8, x8, #58 ldr w0, [x2, x8, lsl #2] ret ``` This patch checks to see if the `SHIFTING` + `AND` operation on load target can be optimized and optimizes it if it can.
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Updated fix for mixing target data op and target op.