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1. SideLine_Zynq SideLine_Zynq Public

   SideLine is a novel power side-channel vector based on delay-line components widely implemented in high-end SoC.

   C 8 4

2. SideLine_STM32MP1 SideLine_STM32MP1 Public

   SideLine is a novel power side-channel vector based on delay-line components widely implemented in high-end SoC.

   C 5 2

3. FaultLine FaultLine Public

   FaultLine is a software-based fault injection attack vector. It uses delay-lines (located in memory controllers) as memory transfer glitch injectors.

   C 3 1

4. vispy vispy Public

   Forked from vispy/vispy

   Main repository for Vispy

   Python