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@SJTU-ECTL

Emerging Computing Technology Laboratory at SJTU

A research group led by Prof. Weikang Qian from SJTU that focuses on emerging computing technologies, such as new computing paradigms and novel devices.

Popular repositories Loading

  1. ALSRAC ALSRAC Public

    ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

    C++ 18 7

  2. GOMIL GOMIL Public

    GOMIL: Global Optimization of Multiplier by Integer Linear Programming

    C++ 12 1

  3. VECBEE VECBEE Public

    VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

    C++ 11 5

  4. DALS DALS Public

    DALS: Delay-Driven Approximate Logic Synthesis

    C++ 6 2

  5. MECALS MECALS Public

    An approximate logic synthesis tool under the maximum error constraint

    Verilog 5

  6. STOCA STOCA Public

    STOCA: Stochastic Circuit Synthesis by Cube Assignment

    C++ 4

Repositories

Showing 10 of 22 repositories
  • MASIM Public

    multi array SIMD IMC scheduler

    SJTU-ECTL/MASIM’s past year of commit activity
    Verilog 1 0 0 0 Updated Dec 24, 2024
  • IMCCompiler Public

    logic compiler for SIMD IMC

    SJTU-ECTL/IMCCompiler’s past year of commit activity
    C++ 1 1 0 0 Updated Dec 24, 2024
  • IMCScheduler Public

    SIMD IMC scheduler target at minimizing memory footprint

    SJTU-ECTL/IMCScheduler’s past year of commit activity
    C++ 1 0 0 0 Updated Dec 24, 2024
  • ALSRAC Public

    ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

    SJTU-ECTL/ALSRAC’s past year of commit activity
    C++ 18 7 3 0 Updated Dec 23, 2024
  • QUADOL Public

    Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs

    SJTU-ECTL/QUADOL’s past year of commit activity
    C++ 0 0 0 0 Updated Nov 27, 2024
  • SCGen Public
    SJTU-ECTL/SCGen’s past year of commit activity
    C++ 0 0 0 0 Updated Mar 11, 2024
  • MECALS Public

    An approximate logic synthesis tool under the maximum error constraint

    SJTU-ECTL/MECALS’s past year of commit activity
    Verilog 5 0 0 0 Updated Apr 27, 2023
  • HEDALS Public

    Highly efficient delay-driven approximate logic synthesis

    SJTU-ECTL/HEDALS’s past year of commit activity
    Verilog 4 BSD-3-Clause 1 0 0 Updated Apr 27, 2023
  • TFASC Public

    TFASC: Target Function Approximation for Stochastic Circuit Minimization

    SJTU-ECTL/TFASC’s past year of commit activity
    C++ 2 0 0 0 Updated May 17, 2022
  • VECBEE Public

    VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis

    SJTU-ECTL/VECBEE’s past year of commit activity
    C++ 11 5 0 0 Updated Mar 8, 2022

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