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add test
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@jumormt
jumormt committed Sep 4, 2024
1 parent 701d502 commit d3cd3e5
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Showing 6 changed files with 233 additions and 91 deletions.
32 changes: 32 additions & 0 deletions Assignment-2/Test2.cpp
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Expand Up @@ -87,10 +87,42 @@ void Test2()
SVFIR::releaseSVFIR();
delete gt;
}

void Test3()
{
// Your current workingspace dir}/Assignment-2/testCase/
std::vector<std::string> moduleNameVec = {"./Assignment-2/testcase/bc/test3.ll"};

SVFModule *svfModule = LLVMModuleSet::getLLVMModuleSet()->buildSVFModule(moduleNameVec);

/// Build Program Assignment Graph (SVFIR)
SVFIRBuilder builder(svfModule);
SVFIR *pag = builder.build();
ICFG *icfg = pag->getICFG();
// If you want to test your own case, plase change the dump name
icfg->dump("./Assignment-2/testcase/dot/test3.ll.icfg");
ICFGTraversal *gt = new ICFGTraversal(pag);
for (const CallICFGNode *src : gt->identifySources())
{
for (const CallICFGNode *snk : gt->identifySinks())
{
gt->reachability(src, snk);
}
}

std::set<std::string> expected = {"START->10->11->12->13->4->5->6->7->14->15->4->5->6->7->16->17->18->END"};
assert(expected == gt->getPaths() && "test3 failed!");
std::cout << "test2 passed!" << "\n";
LLVMModuleSet::releaseLLVMModuleSet();
SVFIR::releaseSVFIR();
delete gt;
}

void Test()
{
Test1();
Test2();
Test3();
}

int main()
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47 changes: 47 additions & 0 deletions Assignment-2/testcase/bc/test3.ll
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@@ -0,0 +1,47 @@
; ModuleID = 'test3.ll'
source_filename = "Assignment-2/testcase/src/test3.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: noinline nounwind uwtable
define dso_local i32 @bar(i32 noundef %s) #0 {
entry:
ret i32 %s
}

; Function Attrs: noinline nounwind uwtable
define dso_local void @foo(ptr noundef %p) #0 {
entry:
store i32 1, ptr %p, align 4
ret void
}

; Function Attrs: noinline nounwind uwtable
define dso_local i32 @main() #0 {
entry:
%a = alloca i32, align 4
%call = call i32 (...) @source()
store i32 %call, ptr %a, align 4
call void @foo(ptr noundef %a)
call void @foo(ptr noundef %a)
%0 = load i32, ptr %a, align 4
call void @sink(i32 noundef %0)
ret i32 0
}

declare i32 @source(...) #1

declare void @sink(i32 noundef) #1

attributes #0 = { noinline nounwind uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3, !4}
!llvm.ident = !{!5}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{i32 7, !"frame-pointer", i32 2}
!5 = !{!"clang version 16.0.4 (https://github.com/llvm/llvm-project ae42196bc493ffe877a7e3dff8be32035dea4d07)"}
96 changes: 48 additions & 48 deletions Assignment-2/testcase/dot/test1.ll.icfg.dot
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Original file line number Diff line number Diff line change
@@ -1,52 +1,52 @@
digraph "ICFG" {
label="ICFG";

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Node0x1aa1d20:s0 -> Node0x1a7a650[style=solid,color=blue];
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Node0x1a70370 -> Node0x1a56230[style=solid];
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Node0x1a56230 -> Node0x1a73420[style=solid];
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Node0x1a73420 -> Node0x1ad4db0[style=solid];
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Node0x1ae28a0 -> Node0x1a992d0[style=solid];
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Node0x1a992d0:s0 -> Node0x1a623c0[style=solid,color=red];
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Node0x1a7a650 -> Node0x1ae4680[style=solid];
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Node0x1ae4680 -> Node0x1a85620[style=solid];
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Node0x1a85620 [shape=record,color=black,label="{IntraICFGNode21 \{fun: main\}\nBinaryOPStmt: [Var28 \<-- (Var27 opcode13 Var19)] \n %inc = add nsw i32 %1, 1 }"];
Node0x1a85620 -> Node0x1ae2040[style=solid];
Node0x1ae2040 [shape=record,color=black,label="{IntraICFGNode22 \{fun: main\}\nStoreStmt: [Var17 \<-- Var28] \n store i32 %inc, ptr %a, align 4 }"];
Node0x1ae2040 -> Node0x1a6a460[style=solid];
Node0x1a6a460 [shape=record,color=black,label="{IntraICFGNode23 \{fun: main\}\nBranchStmt: [ Unconditional branch]\nSuccessor 0 ICFGNode13 \n br label %while.cond, !llvm.loop !6 }"];
Node0x1a6a460 -> Node0x1a73420[style=solid];
Node0x557d0caf48b0 [shape=record,color=purple,label="{GlobalICFGNode0\nCopyStmt: [Var1 \<-- Var0] \n ptr null \{ constant data \}\nAddrStmt: [Var32 \<-- Var3] \n i32 0 \{ constant data \}\nAddrStmt: [Var19 \<-- Var3] \n i32 1 \{ constant data \}\nAddrStmt: [Var4 \<-- Var5] \nFunction: source \nAddrStmt: [Var9 \<-- Var10] \nFunction: sink \nAddrStmt: [Var14 \<-- Var15] \nFunction: main }"];
Node0x557d0caf48b0 -> Node0x557d0cad53d0[style=solid];
Node0x557d0cae4520 [shape=record,color=yellow,label="{FunEntryICFGNode1 \{fun: source\}}"];
Node0x557d0cae4520 -> Node0x557d0cae7de0[style=solid];
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Node0x557d0cae7de0:s0 -> Node0x557d0cadab90[style=solid,color=red];
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Node0x557d0cae24c0 -> Node0x557d0cb5be60[style=solid];
Node0x557d0cadab90 [shape=record,color=yellow,label="{FunEntryICFGNode4 \{fun: sink\}}"];
Node0x557d0cadab90 -> Node0x557d0cb4d7c0[style=solid];
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Node0x557d0cb5bab0:s0 -> Node0x557d0cae24c0[style=solid,color=blue];
Node0x557d0cb5be60 [shape=record,color=black,label="{IntraICFGNode6 \{fun: source\}\n ret void }"];
Node0x557d0cb5be60 -> Node0x557d0cb23ea0[style=solid];
Node0x557d0cb23ea0 [shape=record,color=green,label="{FunExitICFGNode7 \{fun: source\}|{<s0>0x557d0cb24d30}}"];
Node0x557d0cb23ea0:s0 -> Node0x557d0cae80c0[style=solid,color=blue];
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Node0x557d0cb4d7c0 -> Node0x557d0cb5bab0[style=solid];
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Node0x557d0cad53d0 -> Node0x557d0cb6d9e0[style=solid];
Node0x557d0cb6d9e0 [shape=record,color=black,label="{IntraICFGNode10 \{fun: main\}\nAddrStmt: [Var17 \<-- Var18] \n %a = alloca i32, align 4 }"];
Node0x557d0cb6d9e0 -> Node0x557d0cb6d6d0[style=solid];
Node0x557d0cb6d6d0 [shape=record,color=black,label="{IntraICFGNode11 \{fun: main\}\nStoreStmt: [Var17 \<-- Var19] \n store i32 1, ptr %a, align 4 }"];
Node0x557d0cb6d6d0 -> Node0x557d0cb5b2a0[style=solid];
Node0x557d0cb5b2a0 [shape=record,color=black,label="{IntraICFGNode12 \{fun: main\}\nBranchStmt: [ Unconditional branch]\nSuccessor 0 ICFGNode13 \n br label %while.cond }"];
Node0x557d0cb5b2a0 -> Node0x557d0cb3d4a0[style=solid];
Node0x557d0cb3d4a0 [shape=record,color=black,label="{IntraICFGNode13 \{fun: main\}\nLoadStmt: [Var23 \<-- Var17] \n %0 = load i32, ptr %a, align 4 }"];
Node0x557d0cb3d4a0 -> Node0x557d0caff780[style=solid];
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Node0x557d0caff780 -> Node0x557d0cafa290[style=solid];
Node0x557d0cafa290 [shape=record,color=black,label="{IntraICFGNode15 \{fun: main\}\nBranchStmt: [Condition Var24]\nSuccessor 0 ICFGNode16 Successor 1 ICFGNode18 \n br i1 %cmp, label %while.body, label %while.end }"];
Node0x557d0cafa290 -> Node0x557d0cb24d30[style=solid];
Node0x557d0cafa290 -> Node0x557d0cb44070[style=solid];
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Node0x557d0cb24d30:s0 -> Node0x557d0cae4520[style=solid,color=red];
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Node0x557d0cae80c0 -> Node0x557d0cb69c80[style=solid];
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Node0x557d0cb44070 -> Node0x557d0cb013e0[style=solid];
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Node0x557d0cb69c80 -> Node0x557d0cb24bb0[style=solid];
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Node0x557d0cb24bb0 -> Node0x557d0cb711f0[style=solid];
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Node0x557d0cb711f0 -> Node0x557d0cb6d390[style=solid];
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Node0x557d0cb6d390 -> Node0x557d0cb3d4a0[style=solid];
}
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