Skip to content

SaadAliHafiz/Single-cycle-riscv-cpu

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

56 Commits
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Saad Ali Hafiz

18B-025-SE

I am a student of Software Engineering in Usman Institute of technology (UIT). I have built the architecture of a single-cycle RISC-V single core processer and implemented its simulation on logisim.

alt text

Supported Instructions:

supported instruction set is RV32I except privilege instructions

alt text

About

No description, website, or topics provided.

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published