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@SpinalHDL

SpinalHDL

A high level hardware description language

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  1. SpinalHDL SpinalHDL Public

    Scala based HDL

    Scala 1.7k 336

  2. VexRiscv VexRiscv Public

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly 2.5k 421

  3. SpinalTemplateSbt SpinalTemplateSbt Public template

    A basic SpinalHDL project

    Scala 78 65

  4. SpinalWorkshop SpinalWorkshop Public

    Labs to learn SpinalHDL

    Scala 145 39

  5. SpinalDoc-RTD SpinalDoc-RTD Public

    The sources of the online SpinalHDL doc

    Python 25 61

  6. Spinal-bootcamp Spinal-bootcamp Public

    Forked from jijingg/Spinal-bootcamp

    SpinalHDL-tutorial based on Jupyter Notebook

    Jupyter Notebook 43 7

Repositories

Showing 10 of 42 repositories
  • VexiiFirmware Public
    SpinalHDL/VexiiFirmware’s past year of commit activity
    C 0 0 0 0 Updated Dec 23, 2024
  • SpinalDoc-RTD Public

    The sources of the online SpinalHDL doc

    SpinalHDL/SpinalDoc-RTD’s past year of commit activity
    Python 25 CC0-1.0 61 21 (4 issues need help) 7 Updated Dec 23, 2024
  • SpinalHDL Public

    Scala based HDL

    SpinalHDL/SpinalHDL’s past year of commit activity
    Scala 1,692 336 123 (6 issues need help) 29 Updated Dec 20, 2024
  • VexiiRiscv-RTD Public
    SpinalHDL/VexiiRiscv-RTD’s past year of commit activity
    Python 1 CC0-1.0 3 0 1 Updated Dec 20, 2024
  • VexiiRiscv Public

    Like VexRiscv, but, Harder, Better, Faster, Stronger

    SpinalHDL/VexiiRiscv’s past year of commit activity
    Scala 113 MIT 13 13 0 Updated Dec 17, 2024
  • SpinalTemplateSbt Public template

    A basic SpinalHDL project

    SpinalHDL/SpinalTemplateSbt’s past year of commit activity
    Scala 78 65 5 5 Updated Dec 17, 2024
  • NaxRiscv Public
    SpinalHDL/NaxRiscv’s past year of commit activity
    Scala 268 MIT 40 41 0 Updated Dec 11, 2024
  • SpinalDoc Public

    SpinalHDL documentation assets (pictures, slides, ...)

    SpinalHDL/SpinalDoc’s past year of commit activity
    HTML 32 13 0 0 Updated Dec 10, 2024
  • riscv-isa-sim Public Forked from riscv-software-src/riscv-isa-sim

    Spike, a RISC-V ISA Simulator

    SpinalHDL/riscv-isa-sim’s past year of commit activity
    C 1 888 0 1 Updated Dec 9, 2024
  • rvls Public

    RISCV lock-step checker based on Spike

    SpinalHDL/rvls’s past year of commit activity
    C++ 10 1 0 0 Updated Dec 2, 2024
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