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Xyloni

xyloni

A Saxon SoC ver 0.3 implementation for Xyloni

List of some killer features

  • Dual Port RAM
  • Fifo
  • 16 bit External Pipeline Bus
  • SPI bus writing to DAC from on chip RAM

Other Takeaways

  • SoC and user logic are segregated such as to generate two verilog output files. This eases developement effort
  • Charles' code using the full power of Scala is formidable to a hardware engineer. This implementation uses a flat hierarchy and hence hardware engineer friendly
  • Creating an SoC will now be more easy and powerful
  • The lack of a Platform Designer like tool is no more to worry. SaxonSoC is here to your rescue

Repository structure for this board

- hardware/scala/saxon/board/efnix/xyoni : contains SpinalHDL files for user logic and SoC

- software/efinix/xyloni
  - bsp/include : soc.h is generated by SpinalHDL and contains complete address map for the VexRiscV application
  - bsp/linker  : the linker directive. Contains information like RAM size, reset address
  - src         : Contains the C source files for the VexRiscV application
  - build       : Binaries from the VexRiscV application generated by RiscV C compiler. e.g riscv-none-embed-gcc.exe
  - z_etc       : Configuration/setup files for OpenOCD
  - makefile    : Makefile for this project
  
- software/standalone/common
  - riscv64-unknown-elf.mk  : You may set compilation flags here
  - standalone.mk           : The lowest makefile which calls the compiler tools
  
- hardware/synthesis/efinix/xyloni
  - /           : Efinity project file
  - a_verilog   : SpinalHDL generated verilog and Ram initialisation files.
  - ip          : Efinix IP used in this project

How to start

Pre-requisites

SaxonSoc Specific

  1. Build RiscV application : From Eclipse build the RiscV application and generate the .hex file that is required by SpinalHDL to compile SaxsonSoC
  2. Generate SaxonSoc and User Logic : Using SBT generate the verilog and Ram init files. These will be generated inside hardware/synthesis/efinix/xyloni/a_verilog. Also soc.h will be generated inside software/efinix/xyloni/bsp/include
  3. Compile RTL and get bit-stream : Using Efinity do a synthesis, place and route and generate bit-stream
  4. Configure FPGA : Program the FPGA via JTAG or SPI using the Efinity Programmer

That is it. Your are done

  1. Update RAM via OpenOCD : Make changes in your RiscV application. Compile and directly download to FPGA RAM in seconds using Eclipse debugger

Walk-through video

SpinalHDL.on.Xyloni.Promo.mp4

See Full video on Youtube

Ravi Ganesh