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Errata update - ACS support for switch
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- Check if switches in the system support ACS feature
- Errata 611

Signed-off-by: Sujana M <sujana.murali@arm.com>
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Sujana-M committed Sep 18, 2024
1 parent 5ca7feb commit 2bd469a
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1 change: 1 addition & 0 deletions baremetal_app/BsaAcs.inf
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Expand Up @@ -108,6 +108,7 @@
../test_pool/pcie/operating_system/test_os_p039.c
../test_pool/pcie/operating_system/test_os_p040.c
../test_pool/pcie/operating_system/test_os_p042.c
../test_pool/pcie/operating_system/test_os_p043.c
../test_pool/pcie/operating_system/test_os_p061.c
../test_pool/pcie/operating_system/test_os_p062.c
../test_pool/pcie/operating_system/test_os_p063.c
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2 changes: 2 additions & 0 deletions docs/arm_bsa_testcase_checklist.rst
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Expand Up @@ -200,6 +200,8 @@ The below table provides the following details
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|842 |PASID support atleast 16 bits |PCI_PAS_1 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|843 |Switches must support ACS if P2P |PCI_PP_06 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|861 |PCIe Unaligned access |PCI_MM_01, PCI_MM_02, PCI_MM_03 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|862 |No extra address translation |PCI_MM_05, PCI_MM_06, PCI_MM_07 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
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165 changes: 165 additions & 0 deletions test_pool/pcie/operating_system/test_os_p043.c
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@@ -0,0 +1,165 @@
/** @file
* Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**/
#include "val/common/include/acs_val.h"
#include "val/common/include/acs_pe.h"
#include "val/common/include/acs_pcie.h"
#include "val/common/include/acs_memory.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 43)
#define TEST_RULE "PCI_PP_06"
#define TEST_DESC "Switches must support ACS if P2P "

static
void
payload(void)
{

uint32_t bdf;
uint32_t func;
uint32_t pe_index;
uint32_t tbl_index;
uint32_t dp_type;
uint32_t cap_base = 0;
uint32_t test_fails;
uint32_t test_skip = 1;
uint32_t acs_data;
uint32_t data;
uint32_t curr_bdf_failed = 0;
pcie_device_bdf_table *bdf_tbl_ptr;

pe_index = val_pe_get_index_mpid(val_pe_get_mpid());

/* Check If PCIe Hierarchy supports P2P */
if (val_pcie_p2p_support())
{
val_print(ACS_PRINT_DEBUG, "\n PCIe hierarchy does not support P2P. Skipping test", 0);
val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
return;
}

bdf_tbl_ptr = val_pcie_bdf_table_ptr();
test_fails = 0;

/* Check for all the function present in bdf table */
for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
{
bdf = bdf_tbl_ptr->device[tbl_index].bdf;
func = PCIE_EXTRACT_BDF_FUNC(bdf);
dp_type = val_pcie_device_port_type(bdf);

/* Check entry is DP port of a switch
* If the device is an UP port of a switch then,
* acc. to PCIe spec the UP port of switch should
* be a function of a multi-function device */
if ((dp_type == DP) || ((dp_type == UP) && (func > 0)))
{
/* Test runs for atleast one device */
test_skip = 0;
val_print(ACS_PRINT_DEBUG, "\n BDF - 0x%x", bdf);

/* Read the ACS Capability */
if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
val_print(ACS_PRINT_ERR,
"\n ACS Capability not supported, Bdf : 0x%x", bdf);
test_fails++;
continue;
}

val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data);

/* Extract ACS source validation bit */
data = VAL_EXTRACT_BITS(acs_data, 0, 0);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n Source validation not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}
/* Extract ACS translation blocking bit */
data = VAL_EXTRACT_BITS(acs_data, 1, 1);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n Translation blocking not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}
/* Extract ACS P2P request redirect bit */
data = VAL_EXTRACT_BITS(acs_data, 2, 2);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n P2P request redirect not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}
/* Extract ACS P2P completion redirect bit */
data = VAL_EXTRACT_BITS(acs_data, 3, 3);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n P2P completion redirect not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}
/* Extract ACS upstream forwarding bit */
data = VAL_EXTRACT_BITS(acs_data, 4, 4);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n Upstream forwarding not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}

/* Extract ACS Direct Translated P2P bit */
data = VAL_EXTRACT_BITS(acs_data, 6, 6);
if (data == 0) {
val_print(ACS_PRINT_DEBUG,
"\n Direct Translated P2P not supported, Bdf : 0x%x", bdf);
curr_bdf_failed++;
}

if (curr_bdf_failed > 0) {
val_print(ACS_PRINT_ERR,
"\n ACS Capability Check Failed, Bdf : 0x%x", bdf);
curr_bdf_failed = 0;
test_fails++;
}
}
}

if (test_skip == 1) {
val_print(ACS_PRINT_DEBUG, "\n No Downstream Port of Switch found. Skipping device", 0);
val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2));
}
else if (test_fails)
val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
else
val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
}

uint32_t
os_p043_entry(uint32_t num_pe)
{

uint32_t status = ACS_STATUS_FAIL;

num_pe = 1; //This test is run on single processor

status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
if (status != ACS_STATUS_SKIP)
val_run_test_payload(TEST_NUM, num_pe, payload, 0);

/* get the result from all PE and check for failure */
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);

val_report_status(0, ACS_END(TEST_NUM), NULL);

return status;
}
1 change: 1 addition & 0 deletions uefi_app/BsaAcs.inf
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Expand Up @@ -104,6 +104,7 @@
../test_pool/pcie/operating_system/test_os_p038.c
../test_pool/pcie/operating_system/test_os_p039.c
../test_pool/pcie/operating_system/test_os_p042.c
../test_pool/pcie/operating_system/test_os_p043.c
../test_pool/smmu/operating_system/test_os_i001.c
../test_pool/smmu/operating_system/test_os_i002.c
../test_pool/smmu/operating_system/test_os_i003.c
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1 change: 1 addition & 0 deletions uefi_app/BsaAcsMem.inf
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Expand Up @@ -104,6 +104,7 @@
../test_pool/pcie/operating_system/test_os_p038.c
../test_pool/pcie/operating_system/test_os_p039.c
../test_pool/pcie/operating_system/test_os_p042.c
../test_pool/pcie/operating_system/test_os_p043.c
../test_pool/smmu/operating_system/test_os_i001.c
../test_pool/smmu/operating_system/test_os_i002.c
../test_pool/smmu/operating_system/test_os_i003.c
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1 change: 1 addition & 0 deletions val/bsa/include/bsa_acs_pcie.h
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Expand Up @@ -69,6 +69,7 @@ uint32_t os_p038_entry(uint32_t num_pe);
uint32_t os_p039_entry(uint32_t num_pe);
uint32_t os_p041_entry(uint32_t num_pe);
uint32_t os_p042_entry(uint32_t num_pe);
uint32_t os_p043_entry(uint32_t num_pe);

/* Linux test */
uint32_t os_p061_entry(uint32_t num_pe);
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3 changes: 3 additions & 0 deletions val/bsa/src/bsa_execute_test.c
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Expand Up @@ -429,6 +429,9 @@ val_bsa_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
status |= os_p038_entry(num_pe);
status |= os_p039_entry(num_pe);
status |= os_p042_entry(num_pe);
if (g_build_sbsa) {
status |= os_p043_entry(num_pe);
}

#endif

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