S_PCIe_10 - STE.DCP enable and disable (ARM-software#381)

- Enable and disable STE.DCP bit to ensure that Direct Cache Prefetch transactions are permitted Signed-off-by: Sujana M <sujana.murali@arm.com>
Sujana-M · Nov 5, 2024 · eca4621 · eca4621
1 parent 426b6b7
commit eca4621
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diff --git a/val/common/include/acs_smmu.h b/val/common/include/acs_smmu.h
@@ -79,4 +79,6 @@ val_smmu_unmap(smmu_master_attributes_t master);
 void
 val_smmu_dump_eventq(void);
 
+uint32_t val_smmu_config_ste_dcp(smmu_master_attributes_t master, uint32_t value);
+
 #endif
diff --git a/val/common/sys_arch_src/smmu_v3/smmu_reg.h b/val/common/sys_arch_src/smmu_v3/smmu_reg.h
@@ -167,9 +167,11 @@ BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1DSS, 1, 0)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1CIR, 3, 2)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1COR, 5, 4)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1CSH, 7, 6)
+BITFIELD_DECL(uint64_t, STRTAB_STE_1_DCP, 17, 17)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_EATS, 29, 28)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_STRW, 31, 30)
 BITFIELD_DECL(uint64_t, STRTAB_STE_1_SHCFG, 45, 44)
+#define STRTAB_STE_1_DCP_SHIFT      17
 #define STRTAB_STE_1_STRW_NSEL1     0UL
 #define STRTAB_STE_1_STRW_EL2       2UL
 #define STRTAB_STE_1_SHCFG_INCOMING 1UL

diff --git a/val/common/sys_arch_src/smmu_v3/smmu_v3.c b/val/common/sys_arch_src/smmu_v3/smmu_v3.c
@@ -16,6 +16,7 @@
  **/
 #include "smmu_v3.h"
 #include "common/include/acs_smmu.h"
+#include "common/include/val_interface.h"
 
 smmu_dev_t *g_smmu;
 uint32_t    g_smmu_index;
@@ -1161,6 +1162,35 @@ uint64_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt
     return 0;
 }
 
+
+uint32_t val_smmu_config_ste_dcp(smmu_master_attributes_t master_attr, uint32_t value)
+{
+    smmu_master_t *master;
+    smmu_dev_t *smmu;
+    uint64_t *ste;
+    uint32_t dcp_value;
+
+    master = smmu_master_at(master_attr.streamid);
+    if (master == NULL)
+        return ACS_INVALID_INDEX;
+
+    smmu = &g_smmu[master_attr.smmu_index];
+    ste = smmu_strtab_get_ste_for_sid(smmu, master->sid);
+
+    if (value == 1)
+        ste[1] = ste[1] | BITFIELD_SET(STRTAB_STE_1_DCP, value);
+    else
+        ste[1] = ste[1] & BITFIELD_SET(STRTAB_STE_1_DCP, value);
+
+    val_print(ACS_PRINT_INFO, "\n       Dump STE values", 0);
+    dump_strtab(ste);
+
+    dcp_value = (ste[1] >> STRTAB_STE_1_DCP_SHIFT) & 0x1;
+
+    return dcp_value;
+
+}
+
 /**
   @brief Clear stream table entry, free any context descriptor tables and
          page tables corresponding to given master device

diff --git a/val/sbsa/include/sbsa_acs_exerciser.h b/val/sbsa/include/sbsa_acs_exerciser.h
@@ -45,6 +45,7 @@ uint32_t e009_entry(void);
 uint32_t e010_entry(void);
 uint32_t e011_entry(void);
 uint32_t e012_entry(void);
+uint32_t e013_entry(void);
 
 typedef enum {
     CORR_RCVR_ERR = 0x0,

diff --git a/val/sbsa/src/sbsa_execute_test.c b/val/sbsa/src/sbsa_execute_test.c
@@ -583,6 +583,7 @@ val_sbsa_exerciser_execute_tests(uint32_t level)
       status |= e010_entry();
       status |= e011_entry();
       status |= e012_entry();
+      status |= e013_entry();
   }
 
   val_print_test_end(status, "Exerciser");