💾 Motorola 6809 8-bit microprocessor CPU Instruction
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| Motorola |
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| 666 88888 000 99999 |
| 6 8 8 0 0 9 9 |
| 6 8 8 0 0 0 9 9 |
| 666666 88888 0 0 0 999999 |
| 6 6 8 8 0 0 0 9 |
| 6 6 8 8 0 0 9 |
| 66666 88888 000 9999 |
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| 6809 MICROPROCESSOR Instruction Set Summary |
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| _________ _________ |
| _| \__/ |_ ____ |
| Vss |_|1 40|_| Halt <-- |
| ___ _| |_ |
| --> NMI |_|2 39|_| XTAL <-- |
| ___ _| |_ |
| --> IRQ |_|3 38|_| EXTAL <-- |
| ____ _| |_ _____ |
| --> FIRQ |_|4 37|_| Reset <-- |
| _| |_ |
| <-- BS |_|5 36|_| MRDY <-- |
| _| |_ |
| <-- BA |_|6 35|_| Q --> |
| _| |_ |
| Vcc |_|7 34|_| E --> |
| _| |_ ___ ____ |
| <-- A0 |_|8 33|_| DMA/BREQ <-- |
| _| |_ _ |
| <-- A1 |_|9 32|_| R/W --> |
| _| |_ |
| <-- A2 |_|10 6809 31|_| D0 <--> |
| _| |_ |
| <-- A3 |_|11 30|_| D1 <--> |
| _| |_ |
| <-- A4 |_|12 29|_| D2 <--> |
| _| |_ |
| <-- A5 |_|13 28|_| D3 <--> |
| _| |_ |
| <-- A6 |_|14 27|_| D4 <--> |
| _| |_ |
| <-- A7 |_|15 26|_| D5 <--> |
| _| |_ |
| <-- A8 |_|16 25|_| D6 <--> |
| _| |_ |
| <-- A9 |_|17 24|_| D7 <--> |
| _| |_ |
| <-- A10 |_|18 23|_| A15 --> |
| _| |_ |
| <-- A11 |_|19 22|_| A14 --> |
| _| |_ |
| <-- A12 |_|20 21|_| A13 --> |
| |______________________| |
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| Adresses | Description |
|---|---|
| FFF0H to FFF1H | Reserved by Motorola |
| FFF2H to FFF3H | SWI3 instruction interrupt vector |
| FFF4H to FFF5H | SWI2 instruction interrupt vector |
| FFF6H to FFF7H | Fast hardware int. vector (FIRQ) |
| FFF8H to FFF9H | Hardware interrupt vector (IRQ) |
| FFFAH to FFFBH | SWI instruction interrupt vector |
| FFFCH to FFFDH | Non-maskable interrupt vector (NMI) |
| FFFEH to FFFFH | Reset vector |
| Registers | Description |
|---|---|
| A B | Accumulators (8-bit) |
| CC | Condition Code register (8-bit) |
| D | A and B (16-bit, A high, B low) |
| DP | Direct Page register (8-bit) |
| PC | Program Counter (16-bit) |
| S U | System/User stack pointer(16-bit) |
| X Y | Index registers (16-bit) |
| Addressing mode | Description |
|---|---|
| DIRECT | Direct addressing mode |
| EXTEND | Extended addressing mode |
| FCB n | Form Constant Byte |
| FCC 'string' | Form Constant Characters |
| FDB nn | Form Double Byte |
| RMB nn | Reserve Memory Bytes |
| Addressing mode | Description | |
|---|---|---|
| a | I | |
| nn,E | E | |
| [nn] | x | |
| xx,p! | X | |
| [xx,p!] | X | |
| n,D | D | |
| #n | # | |
| #nn | * | |
| m | x | |
| [m] | R |
| Bit | Description | |
|---|---|---|
| CCR | -*01? | Unaffect/affected/reset/set/unknown |
| E | E | Entire flag (Bit 7, if set RTI~s=F) |
| F I | I | FIRQ/IRQ interrupt mask (Bit 6/4) |
| H | H | Half carry (Bit 5) |
| N | N | Negative (Bit 3) |
| Z | Z | Zero (Bit 2) |
| V | V | Overflow (Bit 1) |
| C | C | Carry/borrow (Bit 0) |
| ~ | Description |
|---|---|
| a | Acc A or B (a=A,Op=BXH, a=B,Op=FXH) |
| d s EA | Destination/source/effective addr. |
| i p r | Regs X,Y/regs X,Y,S,U/any register |
| m | Relative address (-126 to +129) |
| n nn | 8/16-bit expression(0 to 255/65535) |
| xx p! | A,B,D,nn/p+,-p,p++,--p (indexed) |
| + - * / | Add/subtract/multiply/divide |
| & ~ v x | AND/NOT/inclusive OR/exclusive OR |
| <- -> <-> | Rotate left/rotate right/exchange |
| [ ] [ ]+ -[ ] | Indirect address/increment/decr. |
| { } | Combination of operands |
| {regs} | If E {PC,U/S,Y,X,DP,B,A,CC}/{PC,CC} |
| (10H) (11H) | Hex opcode to precede main opcode |
| Mnemon. | Op | IHNZVC | IEXD#R | ~ | Description | Notes |
|---|---|---|---|---|---|---|
| ABX | 3A | ------ | X | 3 | Add to Index Register | X=X+B |
| ADCa s | B9 | -***** | XXXXX | 5 | Add with Carry | a=a+s+C |
| ADDa s | BB | -***** | XXXXX | 5 | Add | a=a+s |
| ADDD s | F3 | -***** | XXX*X | 7 | Add to Double acc. | D=D+s |
| ANDa s | B4 | --**0- | XXXXX | 5 | Logical AND | a=a&s |
| ANDCC s | 1C | ?????1 | X | 3 | Logical AND with CCR | CC=CC&s |
| ASL d | 78 | --**** | XXX X | 7 | Arithmetic Shift Left | d=d*2 |
| ASLa | 48 | --**** | X | 2 | Arithmetic Shift Left | a=a*2 |
| ASR d | 77 | --**** | XXX X | 7 | Arithmetic Shift Right | d=d/2 |
| ASRa | 47 | --**** | X | 2 | Arithmetic Shift Right | a=a/2 |
| BCC m | 24 | ------ | x | 3 | Branch if Carry Clear | If C=0 |
| BCS m | 25 | ------ | x | 3 | Branch if Carry Set | If C=1 |
| BEQ m | 27 | ------ | x | 3 | Branch if Equal | If Z=1 |
| BGE m | 2C | ------ | x | 3 | Branch if Great/Equal | If NxV=0 |
| BGT m | 2E | ------ | x | 3 | Branch if Greater Than | If Zv{NxV}=0 |
| BHI m | 22 | ------ | x | 3 | Branch if Higher | If CvZ=0 |
| BHS m | 24 | ------ | x | 3 | Branch if Higher/Same | If C=0 |
| BITa s | B5 | --**0- | XXXXX | 5 | Bit Test accumulator | a&s |
| BLE m | 2F | ------ | x | 3 | Branch if Less/Equal | If Zv{NxV}=1 |
| BLO m | 25 | ------ | x | 3 | Branch if Lower | If C=1 |
| BLS m | 23 | ------ | x | 3 | Branch if Lower/Same | If CvZ=1 |
| BLT m | 2D | ------ | x | 3 | Branch if Less Than | If NxV=1 |
| BMI m | 2B | ------ | x | 3 | Branch if Minus | If N=1 |
| BNE m | 26 | ------ | x | 3 | Branch if Not Equal | If Z=0 |
| BPL m | 2A | ------ | x | 3 | Branch if Plus | If N=0 |
| BRA m | 20 | ------ | x | 3 | Branch Always | PC=m |
| BRN m | 21 | ------ | x | 3 | Branch Never | NOP |
| BSR m | 8D | ------ | x | 7 | Branch to Subroutine | -[S]=PC,BRA |
| BVC m | 28 | ------ | x | 3 | Branch if Overflow Clr | If V=0 |
| BVS m | 29 | ------ | x | 3 | Branch if Overflow Set | If V=1 |
| CLR d | 7F | --0100 | XXX X | 7 | Clear | d=0 |
| CLRa | 4F | --0100 | X | 2 | Clear accumulator | a=0 |
| CMPa s | B1 | --**** | XXXXX | 5 | Compare | a-s |
| CMPD s | B3 | --**** | XXX*X | 8 | Compare Double acc. | D-s (10H) |
| CMPS s | BC | --**** | XXX*X | 8 | Compare Stack pointer | S-s (11H) |
| CMPU s | B3 | --**** | XXX*X | 8 | Compare User stack ptr | U-s (11H) |
| CMPi s | BC | --**** | XXX*X | 7 | Compare | i-s (Y ~s=8) |
| COM d | 73 | --**01 | XXX X | 2 | Complement | d=~d |
| COMa | 43 | --**01 | X | 7 | Complement accumulator | a=~a |
| CWAI n | 3C | E????? | X | K | AND CCR, Wait for int. | CC=CC&n,E=1, |
| DAA | 19 | --**** | X | 2 | Decimal Adjust Acc. | A=BCD format |
| DEC d | 7A | --***- | XXX X | 7 | Decrement | d=d-1 |
| DECa | 4A | --***- | X | 2 | Decrement accumulator | a=a-1 |
| EORa s | B8 | --**0- | XXXXX | 5 | Logical Exclusive OR | a=axs |
| EXG r,r | 1E | ------ | X | 8 | Exchange (r1 size=r2) | r1<->r2 |
| INC d | 7C | --***- | XXX X | 7 | Increment | d=d+1 |
| INCa | 4C | --***- | X | 2 | Increment accumulator | a=a+1 |
| JMP s | 7E | ------ | XXX X | 4 | Jump | PC=EAs |
| JSR s | BD | ------ | XXX X | 8 | Jump to Subroutine | -[S]=PC,JMP |
| LBcc nn | 10 | ------ | x | 5 | Long cond. Branch(~=6) | If cc LBRA |
| LBRA nn | 16 | ------ | x | 5 | Long Branch Always | PC=nn |
| LBSR nn | 17 | ------ | x | 9 | Long Branch Subroutine | -[S]=PC,LBRA |
| LDa s | B6 | --**0- | XXXXX | 5 | Load accumulator | a=s |
| LDD s | FC | --**0- | XXX*X | 6 | Load Double acc. | D=s |
| LDS s | FE | --**0- | XXX*X | 7 | Load Stack pointer | S=s (10H) |
| LDU s | FE | --**0- | XXX*X | 6 | Load User stack ptr | U=s |
| LDi s | BE | --**0- | XXX*X | 6 | Load index register | i=s (Y ~s=7) |
| LEAp s | 3X | ---i-- | xX X | 4 | Load Effective Address | p=EAs(X=0-3) |
| LSL d | 78 | --0*** | XXX X | 7 | Logical Shift Left | d={C,d,0}<- |
| LSLa | 48 | --0*** | X | 2 | Logical Shift Left | a={C,a,0}<- |
| LSR d | 74 | --0*** | XXX X | 7 | Logical Shift Right | d=->{C,d,0} |
| LSRa | 44 | --0*** | X | 2 | Logical Shift Right | d=->{C,d,0} |
| MUL | 3D | ---- | X | B | Multiply | D=A*B |
| NEG d | 70 | -?**** | XXX X | 7 | Negate | d=-d |
| NEGa | 40 | -?**** | X | 2 | Negate accumulator | a=-a |
| NOP | 12 | ------ | X | 2 | No Operation | |
| ORa s | BA | --**0- | XXXXX | 5 | Logical inclusive OR | a=avs |
| ORCC n | 1A | ?????? | X | 3 | Inclusive OR CCR | CC=CCvn |
| PSHS r | 34 | ------ | X | 2 | Push reg(s) (not S) | -[S]={r,...} |
| PSHU r | 36 | ------ | X | 2 | Push reg(s) (not U) | -[U]={r,...} |
| PULS r | 35 | ?????? | X | 2 | Pull reg(s) (not S) | {r,...}=[S]+ |
| PULU r | 37 | ?????? | X | 2 | Pull reg(s) (not U) | {r,...}=[U]+ |
| ROL d | 79 | --**** | XXX X | 7 | Rotate Left | d={C,d}<- |
| ROLa | 49 | --**** | X | 2 | Rotate Left acc. | a={C,a}<- |
| ROR d | 76 | --**** | XXX X | 7 | Rotate Right | d=->{C,d} |
| RORa | 46 | --**** | X | 2 | Rotate Right acc. | a=->{C,a} |
| Mnemon. | Op | IHNZVC | IEXD#R | ~ | Description | Notes |
|---|---|---|---|---|---|---|
| RTI | 3B | -***** | X | 6 | Return from Interrupt | {regs}=[S]+ |
| RTS | 39 | ------ | X | 5 | Return from Subroutine | PC=[S]+ |
| SBCa s | B2 | --**** | XXXXX | 5 | Subtract with Carry | a=a-s-C |
| SEX | 1D | --**-- | X | 2 | Sign Extend | D=B |
| STa d | B7 | --**0- | XXX X | 5 | Store accumultor | d=a |
| STD d | FD | --**0- | XXX X | 6 | Store Double acc. | D=a |
| STS d | FF | --**0- | XXX X | 7 | Store Stack pointer | S=a (10H) |
| STU d | FF | --**0- | XXX X | 6 | Store User stack ptr | U=a |
| STi d | BF | --**0- | XXX X | 6 | Store index register | i=a (Y ~s=7) |
| SUBa s | B0 | --**** | XXXXX | 5 | Subtract | a=a-s |
| SUBD s | B3 | --**** | XXX*X | 7 | Subtract Double acc. | D=D-s |
| SWI | 3F | 1----- | X | J | Software Interrupt 1 | -[S]={regs} |
| SWI2 | 3F | E----- | X | K | Software Interrupt 2 | SWI (10H) |
| SWI3 | 3F | E----- | X | K | Software Interrupt 3 | SWI (11H) |
| SYNC | 13 | ------ | X | 2 | Sync. to interrupt | (min ~s=2) |
| TFR r,r | 1F | ------ | X | 6 | Transfer (r1 size<=r2) | r2=r1 |
| TST s | 7D | --**0- | XXX X | 7 | Test | s |
| TSTa | 4D | --**0- | X | 2 | Test accumulator | a |