Rework top level buffer insertion (bufferinput/bufferoutput) in Resizer.cc #6250
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…for gcd up to cts Signed-off-by: andyfox-rushc <andy@rushc.com>
Signed-off-by: andyfox-rushc <andy@rushc.com>
…eparation of construction of moditerm/modbterm Signed-off-by: andyfox-rushc <andy@rushc.com>
Signed-off-by: andyfox-rushc <andy@rushc.com>
Signed-off-by: andyfox-rushc <andy@rushc.com>
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clang-tidy review says "All clean, LGTM! 👍" |
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@andyfox-rushc , why does QoR change here?
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I believe because of the name change of the net. I will be digging into that to try to avoid the net name change, but it seems very strange to me that the timing result should be sensitive to net name changes.
If one looks at the defs (eg compare buffer_ports1.defok with master and pull request) the diffs are just some net names:
63,65c63,65
< - net1 ( input1 Z ) ( r1 D ) + USE SIGNAL ;
< - net2 ( input2 Z ) ( r2 D ) + USE SIGNAL ;
< - net3 ( output3 A ) ( r3 Q ) + USE SIGNAL ;
- net2 ( input1 Z ) ( r1 D ) + USE SIGNAL ; - net4 ( input2 Z ) ( r2 D ) + USE SIGNAL ; - net6 ( output3 A ) ( r3 Q ) + USE SIGNAL ;
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Its possible someone is hashing or comparing names. Sta itself shouldn't care about names unless it causes an SDC mismatch
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Sorry for the distraction, I will dig into this one and resolve. I realize the issue is with test buffer_ports4.tcl. buffer_ports1.tcl is fine.
Signed-off-by: andyfox-rushc <andy@rushc.com>
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clang-tidy review says "All clean, LGTM! 👍" |
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I am OK with the code change. The QoR change seems odd.
Cho
…On Wed, Nov 27, 2024 at 11:40 AM Matt Liberty ***@***.***> wrote:
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On src/rsz/test/buffer_ports4.ok
<#6250 (comment)>
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Its possible someone is hashing or comparing names. Sta itself shouldn't
care about names unless it causes an SDC mismatch
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(1) Rewrite of the top level port buffering to handle modnet case.
(2) Fix for a latent bug in the bus port member iterator (which was causing the verilog writer to crash -- I am now writing out verilog on each stage of the flow).