Work in-progress
🖥️
Fully self-learnt freelancer interested in low-level languages, embedded systems, hardware design, and artificial intelligence.
- United States of America
- https://thraetaona.github.io/
- https://orcid.org/0000-0003-1393-6804
Highlights
Block or Report
Block or report Thraetaona
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned Loading
-
-
A Simple VHDL Abstraction of an Effi...
A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers 1-------------------------------------------------------------------------------
2-- SPDX-License-Identifier: LGPL-3.0-or-later or CERN-OHL-W-2.0
3--
4-- srl_prescaler.vhd: A Simple VHDL Abstraction of an Efficient Clock
5-- Prescaler Using Cascading Shift Registers.
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.