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VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

130 followers
Santa Cruz, CA
http://vlsida.github.io
mrg+vlsida@ucsc.edu

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OpenRAM OpenRAM Public

An open-source static random access memory (SRAM) compiler.

Python 841 204
openram-docker-image openram-docker-image Public

Shell 5 1
openram-vagrant-image openram-vagrant-image Public

Settings to build a Vagrant image for OpenRAM

Shell 3 1

Repositories

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All C C++ Dockerfile Python Ruby Shell SourcePawn Verilog

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Showing 10 of 28 repositories

vlsida-openroad Public

VLSIDA/vlsida-openroad’s past year of commit activity

Dockerfile 0 0 0 0 Updated Nov 21, 2024
OpenRAM Public
An open-source static random access memory (SRAM) compiler.

VLSIDA/OpenRAM’s past year of commit activity

Python 841 BSD-3-Clause 204 42 (2 issues need help) 8 Updated Nov 14, 2024
OpenROAD Public Forked from The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow

VLSIDA/OpenROAD’s past year of commit activity

Verilog 4 BSD-3-Clause 574 0 0 Updated Oct 10, 2024
openram_testchip Public Forked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io

VLSIDA/openram_testchip’s past year of commit activity

Verilog 9 Apache-2.0 331 0 1 Updated Aug 7, 2024
sky130_sram_macros Public

VLSIDA/sky130_sram_macros’s past year of commit activity

SourcePawn 10 Apache-2.0 11 1 0 Updated Jul 12, 2024
OpenCache Public
An open-source custom cache generator.

VLSIDA/OpenCache’s past year of commit activity

Python 28 BSD-3-Clause 3 1 0 Updated Mar 14, 2024
vlsida-eda Public
Conda recipes for VLSIDA projects.

VLSIDA/vlsida-eda’s past year of commit activity

Shell 5 BSD-3-Clause 0 0 0 Updated Dec 20, 2023
sky130_fd_bd_sram Public

VLSIDA/sky130_fd_bd_sram’s past year of commit activity

0 Apache-2.0 0 0 0 Updated Nov 1, 2023
openram_testchip2 Public

VLSIDA/openram_testchip2’s past year of commit activity

Verilog 2 Apache-2.0 0 0 0 Updated Sep 12, 2023
OpenLane Public Forked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

VLSIDA/OpenLane’s past year of commit activity

SourcePawn 1 Apache-2.0 385 0 0 Updated Jun 6, 2023

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