4bit_magnitude_comparator(dvsd_cmp) RTL2GDS flow

The purpose of this project is to produce a clean GDS (Graphic Design System) Final Layout with all details that are used to print photomasks used in the fabrication of a behavioral RTL (Register-Transfer Level) of an 4bit magnitude comparator, using SkyWater 130nm PDK (Process Design Kit)

Openlane Workflow

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization. For more information check here

OpenLane design stages

Synthesis
- yosys - Performs RTL synthesis
- abc - Performs technology mapping
- OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports
Floorplan and PDN
- init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
- ioplacer - Places the macro input and output ports
- pdn - Generates the power distribution network
- tapcell - Inserts welltap and decap cells in the floorplan
Placement
- RePLace - Performs global placement
- Resizer - Performs optional optimizations on the design
- OpenDP - Perfroms detailed placement to legalize the globally placed components
CTS
- TritonCTS - Synthesizes the clock distribution network (the clock tree)
Routing
- FastRoute - Performs global routing to generate a guide file for the detailed router
- CU-GR - Another option for performing global routing.
- TritonRoute - Performs detailed routing
- SPEF-Extractor - Performs SPEF extraction
GDSII Generation
- Magic - Streams out the final GDSII layout file from the routed def
- Klayout - Streams out the final GDSII layout file from the routed def as a back-up
Checks
- Magic - Performs DRC Checks & Antenna Checks
- Klayout - Performs DRC Checks
- Netgen - Performs LVS Checks
- CVC - Performs Circuit Validity Checks

Installation

Preferred Prerequisites

Preferred Ubuntu OS)
Docker 19.03.12+
GNU Make
Python 3.6+ with PIP
Click, Pyyaml: pip3 install pyyaml click

Setting OpenLane

git clone https://github.com/efabless/openlane.git openlane
cd openlane 
make openlane 
make pdk

Install SKY130 PDK

export PDK_ROOT=<absolute path to where skywater-pdk and open_pdks will reside>

Installed and add this configuration variable

export STD_CELL_LIBRARY=<Library name>

the library names is one of:

sky130_fd_sc_hd
sky130_fd_sc_hs
sky130_fd_sc_ms
sky130_fd_sc_ls
sky130_fd_sc_hdll

you can install all SKY130

make full-pdk

Test

On successful completion of previous step, lets test it by

make test

which shall display the "successful" message.

Note: Go to next steps only after having the successful test.

Next steps

Opening OpenLane in Docker

If docker is installed, if you can see the docker version 19.* and above then docker is present and go to next step else install docker manually

docker --version

you can install docker file following this link

https://docs.docker.com/engine/install/

Pre-layout Simulation

This is how you can simulate your design.

Pre-layout simulation waveform

Running openlane

Once you are sure the docker is present, you have to make mount of the current files in openlane

make mount

Now lets test a design which is already present in openlane/designs type The following directory of design where the design is present is : 'vsdflow/work/tools/openlane_working_dir/openlane/designs/dvsd_cmp'

bash-4:$

./flow.tcl -design dvsd_cmp -tag vanshika_4bit_magnitude_comparator

which shall display the "successful" message after running all the respective tasks.

Synthesis

Synthesis reports


- Printing statistics.

=== dvsd_cmp ===

   Number of wires:                 22
   Number of wire bits:             28
   Number of public wires:           5
   Number of public wire bits:      11
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 20
     $_ANDNOT_                       9
     $_NOR_                          1
     $_ORNOT_                        3
     $_OR_                           3
     $_XNOR_                         1
     $_XOR_                          3


- Printing statistics.

=== dvsd_cmp ===

   Number of wires:                 17
   Number of wire bits:             23
   Number of public wires:           5
   Number of public wire bits:      11
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 15
     sky130_fd_sc_hd__a22oi_2        1
     sky130_fd_sc_hd__inv_2          6
     sky130_fd_sc_hd__nand2_2        1
     sky130_fd_sc_hd__nor2_2         2
     sky130_fd_sc_hd__o211a_2        1
     sky130_fd_sc_hd__o21ba_2        1
     sky130_fd_sc_hd__o221a_2        2
     sky130_fd_sc_hd__o22a_2         1

   Chip area for module '\dvsd_cmp': 106.352000

Yosys synthesis strategies

Floorplanning

cd vsdflow/work/tools/openlane_working_dir/openlane/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/results/floorplan/

magic lef read merged_unpadded.lef def read dvsd_cmp.floorplan.def &

Placement

Placement Analysis

---------------------------------
total displacement         89.0 u
average displacement        1.5 u
max displacement           10.0 u
original HPWL             427.5 u
legalized HPWL            485.6 u
delta HPWL                   14 %

Routing resources analysis:

          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical          630           535          15.08%
met1       Horizontal        840           686          18.33%
met2       Vertical          630           558          11.43%
met3       Horizontal        420           385          8.33%
met4       Vertical          252           214          15.08%
met5       Horizontal         84            70          16.67%
---------------------------------------------------------------

 Final number of vias: 26
 Final usage 3D: 114

Final congestion report:

Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1                535            18            3.36%             0 /  0 /  0
met1               686            18            2.62%             0 /  0 /  0
met2               558             0            0.00%             0 /  0 /  0
met3               385             0            0.00%             0 /  0 /  0
met4               214             0            0.00%             0 /  0 /  0
met5                70             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total             2448            36            1.47%             0 /  0 /  0

Routing

Routing resources analysis:

          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical          630           106          83.17%
met1       Horizontal        840           682          18.81%
met2       Vertical          630           558          11.43%
met3       Horizontal        420           385          8.33%
met4       Vertical          252           214          15.08%
met5       Horizontal         84            70          16.67%
---------------------------------------------------------------

Final congestion report:

Layer         Resource        Demand        Usage (%)    Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1                106             1            0.94%             0 /  0 /  0
met1               682            27            3.96%             0 /  0 /  0
met2               558            36            6.45%             0 /  0 /  0
met3               385             0            0.00%             0 /  0 /  0
met4               214             0            0.00%             0 /  0 /  0
met5                70             0            0.00%             0 /  0 /  0
---------------------------------------------------------------------------------------
Total             2015            64            3.18%             0 /  0 /  0

Complete detail routing:

Total wire length = 459 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 193 um.
Total wire length on LAYER met2 = 241 um.
Total wire length on LAYER met3 = 25 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 150.
Up-via summary (total 150):.

----------------------
 FR_MASTERSLICE      0
            li1     74
           met1     71
           met2      5
           met3      0
           met4      0
----------------------
                   150

Final Summary:

Run Directory: /openLANE_flow/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator
----------------------------------------

Magic DRC Summary:
Source: /openLANE_flow/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/reports/magic//32-magic.drc
Total Magic DRC violations is 0
----------------------------------------

LVS Summary:
Source: /openLANE_flow/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/results/lvs/dvsd_cmp.lvs_parsed.lef.log
LVS reports no net, device, pin, or property mismatches.
Total errors = 0
----------------------------------------

Antenna Summary:
Source: /openLANE_flow/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/reports/routing//34-antenna.rpt
Number of pins violated: 0
Number of nets violated: 0
[INFO]: check full report here: /openLANE_flow/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/reports/final_summary_report.csv
[INFO]: Saving Runtime Environment
[SUCCESS]: Flow Completed Without Fatal Errors.

Layout vs Schematic

Subcircuit summary

Circuit 1: dvsd_cmp                         |Circuit 2: dvsd_cmp                         
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_12                  |sky130_fd_sc_hd__decap_12               
sky130_fd_sc_hd__decap_3                   |sky130_fd_sc_hd__decap_3               
sky130_fd_sc_hd__buf_1                     |sky130_fd_sc_hd__buf_1               
sky130_fd_sc_hd__decap_4                   |sky130_fd_sc_hd__decap_4              
sky130_fd_sc_hd__clkbuf_1                  |sky130_fd_sc_hd__clkbuf_1             
sky130_fd_sc_hd__tapvpwrvgnd_1             |sky130_fd_sc_hd__tapvpwrvgnd_1                
sky130_fd_sc_hd__decap_8                   |sky130_fd_sc_hd__decap_8               
ky130_fd_sc_hd__fill_1                     |sky130_fd_sc_hd__fill_1               
sky130_fd_sc_hd__fill_2                    |sky130_fd_sc_hd__fill_2                 
sky130_fd_sc_hd__inv_2                     |sky130_fd_sc_hd__inv_2                 
sky130_fd_sc_hd__nand2_1                   |sky130_fd_sc_hd__nand2_1               
sky130_fd_sc_hd__decap_6                   |sky130_fd_sc_hd__decap_6             
sky130_fd_sc_hd__o221a_1                   |sky130_fd_sc_hd__o221a_1               
sky130_fd_sc_hd__o21ba_1                   |sky130_fd_sc_hd__o21ba_1                 
sky130_fd_sc_hd__a22oi_1                   |sky130_fd_sc_hd__a22oi_1              
sky130_fd_sc_hd__o22a_1                    |sky130_fd_sc_hd__o22a_1                 
sky130_fd_sc_hd__clkbuf_2                  |sky130_fd_sc_hd__clkbuf_2              
sky130_fd_sc_hd__nor2_1                    |sky130_fd_sc_hd__nor2_1              
sky130_fd_sc_hd__o211a_1                   |sky130_fd_sc_hd__o211a_1
                      
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Magic layout generate

For magic layout generation in magic tool write this in terminal where you ran the above process

bash-4:$

magic dvsd_cmp.mag

Zoom-in view of IP Layout of dvsd_cmp design in Magic Tool.

Zoom-out view of IP Layout of dvsd_cmp design in Magic Tool.

Post-layout simulation

command for post-layout simulation

Post-layout simulation waveform

Steps to reproduce and explore the design

Clone the project using following command

git clone https://github.com/VanshikaTanwar/dvsd_4bit_magnitude_comparator.git

To explore synthesis of the design

make mount
flow.tcl -design dvsd_cmp -synth_explore

To reproduce Pre-layout simulation

cd pre_layout/
iverilog -o dvsd_cmp dvsd_cmp.v test_dvsd_cmp.v
./dvsd_cmp
gtkwave dvsd_cmp.vcd

To explore floorplan

cd vsdflow/work/tools/openlane_working_dir/openlane/designs/dvsd_cmp/runs/vanshika_4bit_magnitude_comparator/results/floorplan/

magic lef read merged_unpadded.lef def read dvsd_cmp.floorplan.def &

To explore placement

cd placement/ 
magic lef read merged.lef def read dvsd_cmp.placement.def &

To explore final layout

cd final_layout/
magic dvsd_cmp.mag

To reproduce Post-layout simulation

cd post_layout/
iverilog -o gls -DFUNCTIONAL -DUNIT_DELAY=#1 gls.v primitives.v sky130_fd_sc_hd.v
./gls
gtkwave gls.vcd

Complete details, logs and results can be found under this folder.

dvsd_cmp
├── config.tcl
├── runs
│   ├── run
│   │   ├── config.tcl
│   │   ├── logs
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── reports
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── cts
│   │   │   ├── cvc
│   │   │   ├── floorplan
│   │   │   ├── klayout
│   │   │   ├── magic
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   └── tmp
│   │       ├── cts
│   │       ├── cvc
│   │       ├── floorplan
│   │       ├── klayout
│   │       ├── magic
│   │       ├── placement
│   │       ├── routing
│   │       └── synthesis

Key points to Remember

Keep the top module name and design name always same, else errors would come in the design.

Area of improvement

To perform spice simulation of the final GDS layout.

References

GitLab/OpenLane workshop
The OpenROAD Project/OpenLane
Ahmed Ghazy and Mohamed Shalan, "OpenLane: The Open-Source Digital ASIC Implementation Flow", Article No.21, Workshop on Open-Source EDA Technology (WOSET), 2020. Paper
YOUTUBE/OpenLane Overview
GitHUB/openlane_build_script
GitLab/OpenLANE-Sky130-Physical-Design-Workshop

Acknowledgement

Kunal Ghosh, Founder, VSD Corp. Pvt. Ltd

Author

Vanshika Tanwar, Bachelor of Technology in Electronics & Communication Engineering,Dronacharya Group of Institutions,Greater Noida, U.P.

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README.md

README.md

4bit_magnitude_comparator(dvsd_cmp) RTL2GDS flow

Table of Contents

Design

Pin Configuration

Openlane Workflow

OpenLane

OpenLane design stages

Installation

Preferred Prerequisites

Setting OpenLane

Install SKY130 PDK

Test

Opening OpenLane in Docker

Pre-layout Simulation

Running openlane

Synthesis

Floorplanning

Placement

Routing

Layout vs Schematic

Magic layout generate

Post-layout simulation

Steps to reproduce and explore the design

Key points to Remember

Area of improvement

References

Acknowledgement

Author

Files

README.md

Latest commit

History

README.md

File metadata and controls

4bit_magnitude_comparator(dvsd_cmp) RTL2GDS flow

Table of Contents

Design

Pin Configuration

Openlane Workflow

OpenLane

OpenLane design stages

Installation

Preferred Prerequisites

Setting OpenLane

Install SKY130 PDK

Test

Opening OpenLane in Docker

Pre-layout Simulation

Running openlane

Synthesis

Floorplanning

Placement

Routing

Layout vs Schematic

Magic layout generate

Post-layout simulation

Steps to reproduce and explore the design

Key points to Remember

Area of improvement

References

Acknowledgement

Author