SPI Robustness #2
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Dridus
approved these changes
Apr 11, 2024
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| /// Disable and then re-enable the SPI peripheral | ||
| #[inline] | ||
| pub fn reset(&mut self) { | ||
| self.config.as_mut().regs.disable(); | ||
| self.config.as_mut().regs.enable(); | ||
| } |
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what's this for? it doesn't reset (ala SWRST), and it's not clear from the manual what if anything it does reset
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My hope is that it will reset the DATA register, so that if we've gotten an overflow fault, there's nothing in the data register to be sent after clearing the fault
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Implemented SPI transfer mods from here: atsamd-rs#657. This prevents write and read loops from getting out of sync and requires one read following every write. Also added a reset function to use in SPI fault recovery (reset flags and clears DATA register).