UVM_TB_For_ShIft_Register

Complete UVM TestBench For Verification Of Shift Register

Main concept here is to understand how to handle delay in scoreboard , you will see ouptput is coming after 3 clock cycle.

Includes : -- Coverage Component -- Scoreboard Component -- TB Architecture

TB Architecture

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
LOG_FILE.log		LOG_FILE.log
README.md		README.md
SHR TB ARCHITECTURE.png		SHR TB ARCHITECTURE.png
coverage_data.html		coverage_data.html
design.sv		design.sv
interface.sv		interface.sv
run.do		run.do
shr_agent.sv		shr_agent.sv
shr_coverage.sv		shr_coverage.sv
shr_driver.sv		shr_driver.sv
shr_env.sv		shr_env.sv
shr_monitor.sv		shr_monitor.sv
shr_scoreboard.sv		shr_scoreboard.sv
shr_sequence.sv		shr_sequence.sv
shr_sequence_item.sv		shr_sequence_item.sv
shr_sequencer.sv		shr_sequencer.sv
shr_test.sv		shr_test.sv
tb_pkg.sv		tb_pkg.sv
testbench.sv		testbench.sv

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