[RWRoute] Clock router for Versal architecture · Xilinx/RapidWright@7470bba

Triggered via pull request November 15, 2024 05:11

synchronize #1102

Status Success

Total duration 30m 47s

Artifacts 4

build.yml

on: pull_request

Matrix: build

Produced during runtime

Name	Size
Java Test Report multi-threaded Expired	314 KB
Java Test Report single-threaded Expired	313 KB
Unit Test Results multi-threaded Expired	245 KB
Unit Test Results single-threaded Expired	244 KB