Merge pull request #847 from Xilinx/2023.1.4

2023.1.4

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.1.3.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.1.4.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.1.3-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.1.4-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2023.1.3-beta
+  RAPIDWRIGHT_VERSION: v2023.1.4-beta
 
 jobs:
   build:

RELEASE_NOTES.TXT

@@ -1,3 +1,62 @@
+============= RapidWright 2023.1.4-beta released on 2023-10-20 ================
+Notes:
+  -Include RapidWright API Lib Javadoc in Gradle Build (#855)
+  - Add com.xilinx.rapidwright.eco.ECOTools package (#850)
+  - More Polynomial Generator improvements (#854)
+  - ReportRouteStatusResult.isFullyRouted() to check >0 logical net found (#852)
+  - Fixes for the PolynomialGenerator (tutorial) (#846)
+  - Test that Design.createModuleInst() copies static sources (#839)
+  - ModuleInst.place() to check both RAMB36/RAMB18 sites for overlap (#841)
+  - PartialRouter preprocessing and clock routing improvements (#843)
+  - Updates to Interchange README.md (#832)
+  - Simplify and make DesignTools.updatePinsIsRouted() more robust (#844)
+  - RouterHelper.invertPossibleGndPinsToVccPins() to not invert BRAM CLKs (#840)
+  - ModuleInst.connect() to leave physical Net alone for pass-thrus (#722)
+  - Unroute site routing when removing a cell (#729)
+  - PartialRouter's global router to not unpreserve sink nodes (#736)
+  - DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
+  - DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
+  - Add DcpToInterchange class (#704)
+  - Add compile step (#733)
+  - Add EdifToLogicalNetlist to MainEntrypoint (#731)
+  - [PhysNetlistReader] Set Cell type for routethru cells (#727)
+  - Fix Javadoc warnings (#723)
+  - Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
+  - Multilevel macro expansion (#726)
+  - TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
+  - DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
+  - Add missing Versal DSP SiteTypeEnum (#842)
+  - [RWRoute] Further fix/cleanup around alternate source pins (#830)
+  - Adding out-of-context flag to RWRoute (#836)
+  - fix a bug in PipelineGeneratorWithRouting.createPipeline() (#837)
+  - Fix verb tense in RWRoute INFO msg (#835)
+  - Enable RWRoute to load Interchange designs from main() (#834)
+  - [VivadoTools] Check for Vivado on PATH first (#831)
+  - [EDIFNetlist] - Ensure Macro Expansion Deep Copies Children  (#828)
+  - Minor RWRoute and UltraScaleClockRouting fixes (#829)
+  - Properly add/remove dual-output pins (#825)
+  - [TestRouteNode] Update comment; swap east and west (#827)
+  - Add VivadoTools.reportRouteStatus() overload for specific net status (#823)
+  - Update link to Discussions forum (#824)
+  - [RWRoute] Only add alternative sources to SiteInst if used (#821)
+  - RouteNode.getPIPsBackToSource() to recognize reversed PIPs (#822)
+  - [PhysNetlistReader] Create FFRoutethruCell-s correctly (#817)
+  - Add test for Design.movePinsToNewNetDeleteOldNet() (#796)
+  - Test Cell.getAllCorrespondingSitePinNames() works for multi-outputs (#792)
+  - [PhysNetlistWriter] No IO site port output BELPins without SitePinInst (#820)
+  - [PhysNetlistWriter] Set PhysPip.setForward() even if not bidir (#819)
+  - [PhysNetlistWriter] Skip output BELPins without cells, and port cells (#818)
+  - Test that Design.createModuleInst() copies static sources (#839)
+  - Design.createModuleInst() to copy STATIC_SOURCE_ SiteInsts properly
+  - Store partname in netlist for new designs
+  - SiteInst.addPin() to trackChanges() when ?_O or ?MUX pin added
+  - Method parameter names preserved in API lib jar
+- API Additions:
+  - com.xilinx.rapidwright.design.Module "public Cell getCell(String cellName)"
+  - com.xilinx.rapidwright.design.Net "public boolean isVCCNet()"
+  - com.xilinx.rapidwright.design.Net "public boolean isGNDNet()"
+  - com.xilinx.rapidwright.design.Net "public boolean isUsedNet()"
+
 ============= RapidWright 2023.1.3-beta released on 2023-09-13 ================
 Notes:
   - Fix DesignTools.getConnectionPIPs() (#809) 

build.gradle

@@ -30,6 +30,7 @@ components["java"].withVariantsFromConfiguration(configurations["testFixturesRun
 
 dependencies {
     api 'com.xilinx.rapidwright:rapidwright-api-lib:' + rapidwright_version
+    api 'com.xilinx.rapidwright:rapidwright-api-lib:' + rapidwright_version + ':javadoc'
 }
 
 sourceSets {

test/src/com/xilinx/rapidwright/design/TestDesign.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021-2022, Xilinx, Inc.
- * Copyright (c) 2022, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Jakob Wenzel, Xilinx Research Labs.
@@ -384,4 +384,28 @@ public void testMovePinsToNewNetDeleteOldNetIntraSiteOnly() {
         Assertions.assertEquals("[H6, B_O, FFMUXB1_OUT1]", si.getSiteWiresFromNet(newNet).toString());
         Assertions.assertTrue(newNet.getPIPs().isEmpty());
     }
+
+    @ParameterizedTest
+    @ValueSource(booleans = {true, false})
+    public void testCreateModuleInstCopiesStaticSource(boolean unrouteStaticNets) {
+        Design design = new Design("testCreateModuleInstCopiesStaticSource", "xcku035");
+
+        Design microblaze = RapidWrightDCP.loadDCP("microblazeAndILA_3pblocks.dcp");
+        final String siteName = "SLICE_X60Y116";
+        Assertions.assertNotNull(microblaze.getSiteInstFromSiteName(siteName));
+
+        Module module = new Module(microblaze, unrouteStaticNets);
+        ModuleInst mi = design.createModuleInst("inst", module);
+        SiteInst si = design.getSiteInstFromSiteName(siteName);
+        Assertions.assertNull(si);
+
+        mi.placeOnOriginalAnchor();
+        si = design.getSiteInstFromSiteName(siteName);
+        if (!unrouteStaticNets) {
+            Assertions.assertNotNull(si);
+            Assertions.assertEquals(mi.getName() + "/STATIC_SOURCE_" + si.getSiteName(), si.getName());
+        } else {
+            Assertions.assertNull(si);
+        }
+    }
 }