Update tests to reflect bug fixes and minor behavior changes (#1110)

Signed-off-by: Chris Lavin <chris.lavin@amd.com>
Xilinx · Nov 22, 2024 · 78346a4 · 78346a4
1 parent 377465b
commit 78346a4
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Showing 2 changed files with 7 additions and 7 deletions.
diff --git a/test/src/com/xilinx/rapidwright/design/TestDesign.java b/test/src/com/xilinx/rapidwright/design/TestDesign.java
@@ -348,7 +348,7 @@ public void testMovePinsToNewNetDeleteOldNet() {
         Assertions.assertTrue(si.routeIntraSiteNet(oldNet, si.getBELPin("A1", "A1"),
                 si.getBELPin(unisim.toString(), "DI0")));
         Assertions.assertEquals("[IN SLICE_X32Y73.A1, OUT SLICE_X32Y73.HQ]", oldNet.getPins().toString());
-        Assertions.assertEquals("[A1, HQ, A5LUT_O5]", si.getSiteWiresFromNet(oldNet).toString());
+        Assertions.assertEquals("[A1, A5LUT_O5, HQ]", si.getSiteWiresFromNet(oldNet).toString());
 
         Net newNet = d.createNet("newNet");
         SitePinInst h6 = newNet.createPin("H6", si);
@@ -362,7 +362,7 @@ public void testMovePinsToNewNetDeleteOldNet() {
         Assertions.assertNull(d.getNet(oldNet.getName()));
         Assertions.assertSame(newNet, d.getNet(newNet.getName()));
         Assertions.assertEquals("[IN SLICE_X32Y73.H6, IN SLICE_X32Y73.A1, OUT SLICE_X32Y73.HQ]", newNet.getPins().toString());
-        Assertions.assertEquals("[H6, A1, HQ, A5LUT_O5]", si.getSiteWiresFromNet(newNet).toString());
+        Assertions.assertEquals("[A1, A5LUT_O5, H6, HQ]", si.getSiteWiresFromNet(newNet).toString());
         Assertions.assertEquals("[INT_X21Y73/INT.VCC_WIRE->>IMUX_E47]", newNet.getPIPs().toString());
     }
 
@@ -389,7 +389,7 @@ public void testMovePinsToNewNetDeleteOldNetIntraSiteOnly() {
         Assertions.assertNull(d.getNet(oldNet.getName()));
         Assertions.assertSame(newNet, d.getNet(newNet.getName()));
         Assertions.assertEquals("[IN SLICE_X32Y73.H6]", newNet.getPins().toString());
-        Assertions.assertEquals("[H6, B_O, FFMUXB1_OUT1]", si.getSiteWiresFromNet(newNet).toString());
+        Assertions.assertEquals("[B_O, FFMUXB1_OUT1, H6]", si.getSiteWiresFromNet(newNet).toString());
         Assertions.assertTrue(newNet.getPIPs().isEmpty());
     }
 

diff --git a/test/src/com/xilinx/rapidwright/design/compare/TestDesignComparator.java b/test/src/com/xilinx/rapidwright/design/compare/TestDesignComparator.java
@@ -149,25 +149,25 @@ public void testDesignComparator() {
         Assertions.assertTrue(net.hasPIPs());
         test2.removeNet(net);
 
-        compareDesign(22, 1, DesignDiffType.NET_MISSING, dc, gold, test2);
+        compareDesign(28, 1, DesignDiffType.NET_MISSING, dc, gold, test2);
 
         Net extra = new Net("extraNet");
         for (PIP p : net.getPIPs()) {
             extra.addPIP(p);
         }
         test2.addNet(extra);
 
-        compareDesign(23, 1, DesignDiffType.NET_EXTRA, dc, gold, test2);
+        compareDesign(29, 1, DesignDiffType.NET_EXTRA, dc, gold, test2);
 
         Assertions.assertTrue(extra.hasPIPs());
         clk.addPIP(extra.getPIPs().get(0));
 
-        compareDesign(24, 1, DesignDiffType.PIP_EXTRA, dc, gold, test2);
+        compareDesign(30, 1, DesignDiffType.PIP_EXTRA, dc, gold, test2);
 
         clk.getPIPs().remove(clk.getPIPs().size() - 1);
         clk.getPIPs().remove(clk.getPIPs().size() - 1);
 
-        compareDesign(24, 1, DesignDiffType.PIP_MISSING, dc, gold, test2);
+        compareDesign(30, 1, DesignDiffType.PIP_MISSING, dc, gold, test2);
 
         if (dc.comparePIPFlags()) {
             clk.getPIPs().get(clk.getPIPs().size() - 1).setIsStub(true);