Support clock routing on Versal devices

Signed-off-by: Wenhao Lin <wenhao.lin@amd.com>
Xilinx · Nov 13, 2024 · 8d7aaf7 · 8d7aaf7
1 parent a3af7dc
commit 8d7aaf7
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diff --git a/src/com/xilinx/rapidwright/router/RouteNode.java b/src/com/xilinx/rapidwright/router/RouteNode.java
@@ -35,6 +35,7 @@
 import com.xilinx.rapidwright.device.PIP;
 import com.xilinx.rapidwright.device.Tile;
 import com.xilinx.rapidwright.device.Wire;
+import com.xilinx.rapidwright.rwroute.RouterHelper;
 
 
 /**
@@ -381,6 +382,19 @@ public ArrayList<PIP> getPIPsBackToSource() {
         return pips;
     }
 
+    public ArrayList<PIP> getPIPsBackToSourceByNodes() {
+        ArrayList<PIP> pips = new ArrayList<>();
+        RouteNode curr = this;
+        while (curr.parent != null) {
+            PIP pip = RouterHelper.findPIPbetweenNodes(Node.getNode(curr.parent), Node.getNode(curr));
+            if (pip != null) {
+                pips.add(pip);
+            }
+            curr = curr.parent;
+        }
+        return pips;
+    }
+
     public Wire[] getWiresInNode() {
         return Node.getWiresInNode(getTile(),getWire());
     }