Merge pull request #974 from Xilinx/2023.2.2

2023.2.2

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.2.1.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2023.2.2.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.2.1-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2023.2.2-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2023.2.1-beta
+  RAPIDWRIGHT_VERSION: v2023.2.2-beta
 
 jobs:
   build:

RELEASE_NOTES.TXT

@@ -1,3 +1,59 @@
+============= RapidWright 2023.2.2-beta released on 2023-04-03 ================
+Notes:
+  - Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (#977)
+  - Remove some pre-2023.2.2 workarounds (#978)
+  - [RWRoute] Fix logical driver flag setting for DCP write (#979)
+  - Add explicit use case for a Jython script in --help (#980)
+  - [VivadoTools] Add placeDesign() and getWorstSetupSlack() (#975)
+  - [RWRoute] Consider all nets in timing-driven routing (#976)
+  - [DCP] Test Design.writeCheckpoint() when using existing EDIF (#965)
+  - Work around for multi-inverter BEL in DSP58 (#969)
+  - [DesignTools.makeBlackBox()] Fix for #967 (#970)
+  - [RWRoute,PhysNetlistReader] Set logical driver on PIPs (#973)
+  - [SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking (#972)
+  - [EDIFTokenizer] Account for byte size of UTF-8 characters correctly (#962)
+  - [VivadoTools] writeBitstream to not delete DCP parent dir (+more) (#955)
+  - [RWRoute] Preserve [A-H]_O node when [A-H]MUX used as static src (#954)
+  - [GlobalSignalRouter] No intra site routing for new static source pins (#953)
+  - [EDIFPropertyValue] Fix getBooleanValue() NPE (#952)
+  - [PhysNetlistReader] Fix checkConstantRoutingAndNetNaming() (#951)
+  - [RWRoute] When removing unused source SPI restore intra-site routing (#949)
+  - [RWRoute] Tidy up createNetWrapperAndConnections() (#950)
+  - Fix EDIFPropertyValue.getBooleanValue() (#948)
+  - [RWRoute] Replace main src with altsrc if main is unused (#945)
+  - [RWRoute] Fix comment Eastern -> Western (#943)
+  - RouterHelper.invertPossibleGndPinsToVccPins() to invert static LUT inputs (#910)
+  - [TestRWRoute] Stop skipping some tests when < 8GB (#941)
+  - Temporary workaround to clear logical net after Net.rename() (#942)
+  - Known failing test for EDIFHierPortInst.getRoutedSitePinInst() (#577)
+  - Known failing test for Tile.getSites() result different to Vivado (#745)
+  - Known failing test for BITSLICE_CONTROL output pin projection (#559)
+  - Add known failing testcase for #756 (#758)
+  - Update RWRouteConfig.java (#940)
+  - [RWRoute] Add --lutRoutethru option (#932)
+  - [RWRoute] Do not pin swap SRL (shift register) cells (#939)
+  - [LUTTools] LUT pin swapping fixes (#938)
+  - Net.rename() to clear logical hier net
+  - Fix regarding issue around bitstream header
+  - Fixes issue when site wire lacks GND tag 
+
+API Additions:
+  - com.xilinx.rapidwright.bitstream.Bitstream "public boolean writeBitstream(Path path)"
+  - com.xilinx.rapidwright.bitstream.Frame "public List<BitLocation> getDiff(Frame otherFrame)"
+  - com.xilinx.rapidwright.design.Cell "public static final String LOCKED = "<LOCKED>";
+  - com.xilinx.rapidwright.design.Cell "public static final String PORT_TYPE = "<PORT>";
+  - com.xilinx.rapidwright.design.Cell "public boolean isPortCell()"
+  - com.xilinx.rapidwright.design.Cell "public String getPropertyValueString(String key)"
+  - com.xilinx.rapidwright.design.Design "public void writeCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
+  - com.xilinx.rapidwright.design.Design "public void writeCheckpoint(Path dcpFileName, Path edfFileName, CodePerfTracker t)"
+  - com.xilinx.rapidwright.design.Design "public void detachNetlist(Predicate<Cell> preserveCellProperties)"
+  - com.xilinx.rapidwright.device.BEL "public static BEL getBEL(Device device, SiteTypeEnum siteTypeEnum, String belName)"
+  - com.xilinx.rapidwright.device.PIP "public boolean isArcInverted()"
+  - com.xilinx.rapidwright.device.PIP "public void setIsLogicalDriver(boolean isLogicalDriver)"
+  - com.xilinx.rapidwright.device.SitePIP "public int getIndex()"
+  - com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"
+
+
 ============= RapidWright 2023.2.1-beta released on 2023-01-10 ================
 Notes:
   - Add EDIFHierCellInst.isUniquified() (#918)

src/com/xilinx/rapidwright/design/DesignTools.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017-2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Xilinx Research Labs.
@@ -81,7 +81,6 @@
 import com.xilinx.rapidwright.edif.EDIFPortInst;
 import com.xilinx.rapidwright.edif.EDIFPropertyValue;
 import com.xilinx.rapidwright.edif.EDIFTools;
-import com.xilinx.rapidwright.interchange.PhysNetlistWriter;
 import com.xilinx.rapidwright.placer.blockplacer.BlockPlacer2Impls;
 import com.xilinx.rapidwright.placer.blockplacer.ImplsInstancePort;
 import com.xilinx.rapidwright.placer.blockplacer.ImplsPath;
@@ -1823,8 +1822,6 @@ public static void makeBlackBox(Design d, EDIFHierCellInst hierarchicalCell) {
             if (!net.rename(e.getValue())) {
                 throw new RuntimeException("ERROR: Failed to rename net '" + net.getName() + "'");
             }
-            // TODO: Remove workaround below when >2023.2.1
-            net.setLogicalHierNet(null);
             netsToKeep.add(net.getName());
         }
 
@@ -3143,8 +3140,7 @@ public static void makePhysNetNamesConsistent(Design design) {
                     if (parentPhysNet != null) {
                         // Fall through
                     } else if (net.rename(parentHierNet.getHierarchicalNetName())) {
-                        // TODO: Remove workaround below when >2023.2.1
-                        net.setLogicalHierNet(null);
+                        // Fall through
                     } else {
                         System.out.println("WARNING: Failed to adjust physical net name " + net.getName());
                     }
@@ -3988,7 +3984,7 @@ public static void prepareShellBlackBoxForRouting(Design design) {
                     }
                 }
                 if (c.getBEL().isFF()) {
-                    if(c.getName().equals(PhysNetlistWriter.LOCKED)) continue;
+                    if(c.getName().equals(Cell.LOCKED)) continue;
                     String belName = c.getBELName();
                     char letter = belName.charAt(0);
                     boolean isFF2 = belName.charAt(belName.length() - 1) == '2';

src/com/xilinx/rapidwright/design/tools/RelocationTools.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021-2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Eddie Hung, Xilinx Research Labs.
@@ -35,7 +35,6 @@
 import com.xilinx.rapidwright.device.Tile;
 import com.xilinx.rapidwright.edif.EDIFHierCellInst;
 import com.xilinx.rapidwright.edif.EDIFNetlist;
-import com.xilinx.rapidwright.interchange.PhysNetlistWriter;
 import com.xilinx.rapidwright.util.Utils;
 
 import java.util.ArrayList;
@@ -130,7 +129,7 @@ public static boolean relocate(Design design,
         for (SiteInst si : siteInsts) {
             for (Cell c : si.getCells()) {
                 if (!c.isLocked() && !c.isRoutethru() && !cells.contains(c)
-                        && !c.getType().equals(PhysNetlistWriter.PORT)) {
+                        && !c.isPortCell()) {
                     System.out.println("ERROR: Failed to relocate SiteInst '" + si.getName()
                             + "' as it contains Cells both inside and outside of '" + instanceName + "'");
                     error = true;

src/com/xilinx/rapidwright/interchange/PhysNetlistReader.java

@@ -247,7 +247,7 @@ protected void readPlacement(PhysNetlist.Reader physNetlist) {
                 Cell c = siteInst.getCell(belName);
                 if (c == null) {
                     BEL bel = siteInst.getBEL(belName);
-                    c = new Cell(PhysNetlistWriter.LOCKED, bel);
+                    c = new Cell(Cell.LOCKED, bel);
                     c.setType(strings.get(placement.getType()));
                     c.setBELFixed(placement.getIsBelFixed());
                     c.setNullBEL(bel == null);
@@ -258,7 +258,7 @@ protected void readPlacement(PhysNetlist.Reader physNetlist) {
                 // c Alternative Blocked Site Type // TODO
             } else if (physType == PhysCellType.PORT) {
                 Cell portCell = new Cell(cellName,siteInst.getBEL(belName));
-                portCell.setType(PhysNetlistWriter.PORT);
+                portCell.setType(Cell.PORT_TYPE);
                 siteInst.addCell(portCell);
                 portCell.setBELFixed(placement.getIsBelFixed());
                 portCell.setSiteFixed(placement.getIsSiteFixed());

src/com/xilinx/rapidwright/interchange/PhysNetlistWriter.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2020-2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Xilinx Research Labs.
@@ -94,10 +94,6 @@ public class PhysNetlistWriter {
      */
     public static boolean VERBOSE_PHYSICAL_NET_ROUTING = true;
 
-    public static final String LOCKED = "<LOCKED>";
-    public static final String PORT = "<PORT>";
-
-
     protected static void writeSiteInsts(PhysNetlist.Builder physNetlist, Design design,
                                          StringEnumerator strings) {
         Builder<SiteInstance.Builder> siteInsts = physNetlist.initSiteInsts(design.getSiteInsts().size());
@@ -112,10 +108,10 @@ protected static void writeSiteInsts(PhysNetlist.Builder physNetlist, Design des
 
     protected static String getUniqueLockedCellName(Cell cell, Map<String,PhysCellType> physCells) {
         String cellName = cell.getName();
-        if (cellName.equals(LOCKED)) {
-            cellName = cell.getSiteName() + "_" + cell.getBELName() + "_" + LOCKED;
+        if (cellName.equals(Cell.LOCKED)) {
+            cellName = cell.getSiteName() + "_" + cell.getBELName() + "_" + Cell.LOCKED;
             physCells.put(cellName,PhysCellType.LOCKED);
-        } else if (cell.getType().equals(PORT)) {
+        } else if (cell.isPortCell()) {
             physCells.put(cellName,PhysCellType.PORT);
         }
         return cellName;
@@ -138,7 +134,7 @@ public static void writePlacement(PhysNetlist.Builder physNetlist, Design design
                 allCells.add(cell);
                 if (!cell.isPlaced()) continue;
                 String cellName = cell.getName();
-                if (cellName.equals(PhysNetlistWriter.LOCKED)) continue;
+                if (cellName.equals(Cell.LOCKED)) continue;
                 Cell multiCell = design.getCell(cellName);
                 if (multiCell == null) {
                     assert(cell.isFFRoutethruCell());
@@ -363,7 +359,7 @@ public static void extractIntraSiteRouting(Net net, List<RouteBranchNode> nodes,
                         assert(bel.isLUT() || // LUTs can be a GND or VCC source
                                 (net.isGNDNet() && bel.isGndSource()) ||
                                 (net.isVCCNet() && bel.isVccSource()));
-                    } else if (cell.getType().equals(PORT)) {
+                    } else if (cell.isPortCell()) {
                         if (Utils.isIOB(siteInst)) {
                             assert(belPin.isBidir());
                             assert(bel.getName().equals("PAD"));

test/shared/com/xilinx/rapidwright/util/VivadoToolsHelper.java

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Author: Eddie Hung, Advanced Micro Devices, Inc.
+ *
+ * This file is part of RapidWright.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+package com.xilinx.rapidwright.util;
+
+import com.xilinx.rapidwright.design.Design;
+import org.junit.jupiter.api.Assertions;
+
+import java.nio.file.Path;
+
+public class VivadoToolsHelper {
+    public static void assertFullyRouted(Design design) {
+        if (!FileTools.isVivadoOnPath()) {
+            return;
+        }
+
+        ReportRouteStatusResult rrs = VivadoTools.reportRouteStatus(design);
+        Assertions.assertTrue(rrs.isFullyRouted());
+    }
+
+    public static void assertFullyRouted(Path dcp) {
+        if (!FileTools.isVivadoOnPath()) {
+            return;
+        }
+
+        ReportRouteStatusResult rrs = VivadoTools.reportRouteStatus(dcp);
+        Assertions.assertTrue(rrs.isFullyRouted());
+    }
+}

test/src/com/xilinx/rapidwright/design/TestDCPSave.java

@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (c) 2022, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022, 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Xilinx Research Labs.
@@ -24,6 +24,12 @@
 
 import java.nio.file.Path;
 
+import com.xilinx.rapidwright.edif.EDIFNetlist;
+import com.xilinx.rapidwright.edif.EDIFTools;
+import com.xilinx.rapidwright.support.RapidWrightDCP;
+import com.xilinx.rapidwright.util.VivadoTools;
+import com.xilinx.rapidwright.util.VivadoToolsHelper;
+import org.junit.jupiter.api.Assertions;
 import org.junit.jupiter.api.Test;
 import org.junit.jupiter.api.io.TempDir;
 
@@ -32,15 +38,19 @@
 import com.xilinx.rapidwright.edif.EDIFCell;
 import com.xilinx.rapidwright.edif.EDIFCellInst;
 import com.xilinx.rapidwright.edif.EDIFLibrary;
+import org.junit.jupiter.params.ParameterizedTest;
+import org.junit.jupiter.params.provider.ValueSource;
 
 public class TestDCPSave {
 
-    @Test
-    public void testDCPSave(@TempDir Path tempDir) {
+    @ParameterizedTest
+    @ValueSource(booleans = { true, false })
+    public void testDCPSave(boolean detachNetlist, @TempDir Path tempDir) {
         // Taken from example provided by https://github.com/nqdtan in #548
         Design d = new Design("test", "xcvc1902-vsvd1760-2MP-e-S");
-        EDIFLibrary plib = d.getNetlist().getHDIPrimitivesLibrary();
-        EDIFCell top = d.getNetlist().getTopCell();
+        EDIFNetlist n = d.getNetlist();
+        EDIFLibrary plib = n.getHDIPrimitivesLibrary();
+        EDIFCell top = n.getTopCell();
         EDIFCell ec0 = new EDIFCell(plib, "LUT6CY");
         EDIFCell ec1 = new EDIFCell(plib, "LUTCY1");
         EDIFCell ec2 = new EDIFCell(plib, "LUTCY2");
@@ -71,7 +81,26 @@ public void testDCPSave(@TempDir Path tempDir) {
         c2.addPinMapping("A4", "I3");
         c2.addPinMapping("A5", "I4");
         c2.addPinMapping("O5", "O");
-
-        d.writeCheckpoint(tempDir.resolve("tmp.dcp"));        
+
+        if (detachNetlist) {
+            EDIFTools.writeEDIFFile(tempDir.resolve("tmp.edf"), n, d.getPartName());
+            d.detachNetlist();
+            d.writeCheckpoint(tempDir.resolve("tmp.dcp"), tempDir.resolve("tmp.edf"), null);
+        } else {
+            d.writeCheckpoint(tempDir.resolve("tmp.dcp"));
+        }
+    }
+
+    @Test
+    public void testWriteCheckpointPreWrittenEDIF(@TempDir Path tempDir) {
+        Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp");
+
+        Path edfPath = tempDir.resolve("tmp.edf");
+        EDIFTools.writeEDIFFile(edfPath, design.getNetlist(), design.getPartName());
+        design.detachNetlist();
+        Path dcpPath = tempDir.resolve("tmp.dcp");
+        design.writeCheckpoint(dcpPath, edfPath, null);
+
+        VivadoToolsHelper.assertFullyRouted(design);
     }
 }

test/src/com/xilinx/rapidwright/design/tools/TestLUTTools.java

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022, Xilinx, Inc.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Xilinx Research Labs.
@@ -40,6 +40,7 @@
 import com.xilinx.rapidwright.rwroute.TestRWRoute;
 import com.xilinx.rapidwright.support.LargeTest;
 import com.xilinx.rapidwright.support.RapidWrightDCP;
+import com.xilinx.rapidwright.util.VivadoToolsHelper;
 import org.junit.jupiter.api.Assertions;
 import org.junit.jupiter.api.Test;
 
@@ -165,7 +166,7 @@ public void testUpdateLutPinSwapsFromPIPsWithRWRoute(String path, boolean lutPin
             }
             TestRWRoute.assertAllSourcesRoutedFlagSet(design);
             TestRWRoute.assertAllPinsRouted(design);
-            TestRWRoute.assertVivadoFullyRouted(design);
+            VivadoToolsHelper.assertFullyRouted(design);
         } finally {
             System.setProperty("rapidwright.rwroute.lutPinSwapping.deferIntraSiteRoutingUpdates", "false");
         }

test/src/com/xilinx/rapidwright/eco/TestECOTools.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Eddie Hung, Advanced Micro Devices, Inc.
@@ -40,13 +40,12 @@
 import com.xilinx.rapidwright.edif.EDIFNetlist;
 import com.xilinx.rapidwright.edif.EDIFPortInst;
 import com.xilinx.rapidwright.router.Router;
-import com.xilinx.rapidwright.rwroute.TestRWRoute;
 import com.xilinx.rapidwright.support.RapidWrightDCP;
 import com.xilinx.rapidwright.util.FileTools;
 import com.xilinx.rapidwright.util.ReportRouteStatusResult;
 import com.xilinx.rapidwright.util.VivadoTools;
+import com.xilinx.rapidwright.util.VivadoToolsHelper;
 import org.junit.jupiter.api.Assertions;
-import org.junit.jupiter.api.Assumptions;
 import org.junit.jupiter.api.Disabled;
 import org.junit.jupiter.api.Test;
 
@@ -467,7 +466,7 @@ public void testCreateAndPlaceInlineCellOnInputPin() {
         Assertions.assertEquals(net0, lut1.getSitePinFromLogicalPin("I0", null).getNet());
         Assertions.assertNotEquals(net0, lut1.getSitePinFromLogicalPin("O", null).getNet());
 
-        TestRWRoute.assertVivadoFullyRouted(d);
+        VivadoToolsHelper.assertFullyRouted(d);
     }
 
     @Test