Skip another assert for Versal

Signed-off-by: Eddie Hung <eddie.hung@amd.com>
Xilinx · Nov 8, 2024 · cc9bee5 · cc9bee5
1 parent cc77e12
commit cc9bee5
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/com/xilinx/rapidwright/rwroute/RWRoute.java b/src/com/xilinx/rapidwright/rwroute/RWRoute.java
@@ -1839,7 +1839,9 @@ private void exploreAndExpand(ConnectionState state, RouteNode rnode) {
                     case EXCLUSIVE_SINK_WEST:
                         assert(childRNode.getType() != RouteNodeType.EXCLUSIVE_SINK_EAST || rnode.getType() == RouteNodeType.LOCAL_EAST);
                         assert(childRNode.getType() != RouteNodeType.EXCLUSIVE_SINK_WEST || rnode.getType() == RouteNodeType.LOCAL_WEST);
-                        assert(childRNode.getType() != RouteNodeType.EXCLUSIVE_SINK || rnode.getType() == RouteNodeType.LOCAL);
+                        assert(childRNode.getType() != RouteNodeType.EXCLUSIVE_SINK || rnode.getType() == RouteNodeType.LOCAL ||
+                                // FIXME:
+                                design.getSeries() == Series.Versal);
                         if (!isAccessibleSink(childRNode, connection)) {
                             continue;
                         }