2024.2.0

.classpath

@@ -33,9 +33,9 @@
 	<classpathentry kind="lib" path="jars/kryo-5.2.1.jar"/>
 	<classpathentry kind="lib" path="jars/minlog-1.3.1.jar"/>
 	<classpathentry kind="lib" path="jars/jython-standalone-2.7.2.jar"/>
-	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.1.3.jar">
+	<classpathentry kind="lib" path="jars/rapidwright-api-lib-2024.2.0-rc1.jar">
 		<attributes>
-			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.1.3-javadoc.jar!/"/>
+			<attribute name="javadoc_location" value="jar:platform:/resource/RapidWright/jars/rapidwright-api-lib-2024.2.0-rc1-javadoc.jar!/"/>
 		</attributes>
 	</classpathentry>
 	<classpathentry kind="lib" path="jars/jgrapht-core-1.3.0.jar"/>

.github/workflows/build.yml

@@ -5,7 +5,7 @@ on:
   pull_request:
 
 env:
-  RAPIDWRIGHT_VERSION: v2024.1.3-beta
+  RAPIDWRIGHT_VERSION: v2024.2.0-rc1-beta
 
 jobs:
   build:

src/com/xilinx/rapidwright/design/DesignTools.java

@@ -289,7 +289,7 @@ public static ArrayList<BELPin> getCorrespondingBELInputPins(BELPin outputPin, S
                     Net net = inst.getNetFromSiteWire(siteWireName);
                     if (net == null) continue;
                     if (net.isStaticNet()) continue;
-                    if (!cell.getPinMappingsP2L().containsKey(pin.getName())) continue;
+                    if (!cell.usesPhysicalPin(pin.getName())) continue;
                     inputs.add(pin);
                 }
                 break;
@@ -325,7 +325,8 @@ public static ArrayList<BELPin> getCorrespondingBELOutputPins(BELPin inputPin, S
             if (net == null) continue;
             if (net.isStaticNet()) continue;
             if (net.getName().equals(Net.USED_NET)) continue;
-            if (!cell.getPinMappingsP2L().containsKey(pin.getName())) continue;
+            if (!cell.usesPhysicalPin(pin.getName()))
+                continue;
             outputs.add(pin);
         }
 
@@ -445,7 +446,7 @@ public static String invertLutInput (Cell lut, String physicalPinName) {
         long oldVal = new BigInteger(hexValueStr, 16).longValue();
         int numLutRows = Integer.parseInt(numLutRowsStr);
         int numInput = (int)(Math.log(numLutRows)/Math.log(2));
-        String logicalPinName = lut.getPinMappingsP2L().get(physicalPinName);
+        String logicalPinName = lut.getLogicalPinMapping(physicalPinName);
         int invertCol = getInvertCol(logicalPinName.substring(logicalPinName.length()-1));
         if (invertCol == -1) {
             System.err.println("Inverted Column is -1 is Function DesignTools.invertLutInput");
@@ -1563,12 +1564,11 @@ public static List<SitePinInst> unrouteCellPinSiteRouting(Cell cell, String logi
                             if (otherCell.isRoutethru()) {
                                 BELPin otherPin = null;
                                 if (pin.isOutput()) {
-                                    assert(otherCell.getPinMappingsP2L().size() == 1);
-                                    String otherPinName = otherCell.getPinMappingsP2L().keySet().iterator().next();
-                                    otherPin = pin.getBEL().getPin(otherPinName);
+                                    assert (otherCell.getUsedPhysicalPinsCount() == 1);
+                                    otherPin = otherCell.getFirstPhysicalPinMapping().getFirst();
                                 } else {
                                     // Make sure we are coming in on the routed-thru pin
-                                    String otherPinName = otherCell.getPinMappingsP2L().keySet().iterator().next();
+                                    String otherPinName = otherCell.getFirstPhysicalPinMapping().getFirst().getName();
                                     if (pin.getName().equals(otherPinName)) {
                                         otherPin = LUTTools.getLUTOutputPin(pin.getBEL());
                                     }
@@ -1777,7 +1777,8 @@ public static void makeBlackBox(Design d, EDIFHierCellInst hierarchicalCell) {
             }
 
             // Remove all physical nets first
-            for (String logPin : c.getPinMappingsP2L().values()) {
+            for (String logPin : c.getPhysicalPinMappings()) {
+                if (logPin == null) continue;
                 List<SitePinInst> removePins = unrouteCellPinSiteRouting(c, logPin);
                 for (SitePinInst pin : removePins) {
                     pinsToRemove.computeIfAbsent(pin.getNet(), $ -> new HashSet<>()).add(pin);
@@ -1971,7 +1972,7 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
                     }
 
                     Cell newCell = c.copyCell(newCellName, cellInst);
-                    design.placeCell(newCell, newSiteInst.getSite(), c.getBEL(), c.getPinMappingsP2L());
+                    design.placeCell(newCell, newSiteInst.getSite(), c.getBEL(), c.getPhysicalPinMappings());
                 }
 
                 for (SitePIP sitePIP : si.getUsedSitePIPs()) {
@@ -2299,8 +2300,8 @@ public static List<String> getAllRoutedSitePinsFromPhysicalPin(Cell cell, Net ne
                             bel.getName().endsWith("_IMR")) {
                         Cell possibleRouteThru = inst.getCell(bel);
                         if (possibleRouteThru != null && possibleRouteThru.isRoutethru()) {
-                            String routeThru = possibleRouteThru.getPinMappingsP2L().keySet().iterator().next();
-                            queue.add(bel.getPin(routeThru));
+                            BELPin routeThru = possibleRouteThru.getFirstPhysicalPinMapping().getFirst();
+                            queue.add(routeThru);
                         }
                     }
                 }
@@ -2977,14 +2978,19 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
         }
 
         EDIFHierCellInst cellInst = destNetlist.getHierCellInstFromName(copy.getName());
-        for (Entry<String,String> e : copy.getPinMappingsP2L().entrySet()) {
-            EDIFPortInst portInst = cellInst.getInst().getPortInst(e.getValue());
+        String[] physPinNames = copy.getPhysicalPinMappings();
+        for (int i = 0; i < physPinNames.length; i++) {
+            String logPinName = physPinNames[i];
+            if (logPinName == null) continue;
+            String physPinName = copy.getBEL().getPin(i).getName();
+
+            EDIFPortInst portInst = cellInst.getInst().getPortInst(logPinName);
             if (portInst == null) continue;
             EDIFNet edifNet = portInst.getNet();
 
             String netName = new EDIFHierNet(cellInst.getParent(), edifNet).getHierarchicalNetName();
 
-            String siteWireName = orig.getSiteWireNameFromPhysicalPin(e.getKey());
+            String siteWireName = orig.getSiteWireNameFromPhysicalPin(physPinName);
             Net origNet = origSiteInst.getNetFromSiteWire(siteWireName);
             if (origNet == null) continue;
             Net net = null;
@@ -3001,7 +3007,7 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
                 }
             }
 
-            BELPin curr = copy.getBEL().getPin(e.getKey());
+            BELPin curr = copy.getBEL().getPin(physPinName);
             dstSiteInst.routeIntraSiteNet(net, curr, curr);
             boolean routingForward = curr.isOutput();
             Queue<BELPin> q = new LinkedList<BELPin>();
@@ -3040,7 +3046,7 @@ private static void copySiteRouting(Cell copy, Cell orig, Map<String,String> src
                             Cell rtCopy = tmpCell
                                     .copyCell(newCellName, tmpCell.getEDIFHierCellInst(), dstSiteInst);
                             dstSiteInst.getCellMap().put(belName, rtCopy);
-                            for (String belPinName : rtCopy.getPinMappingsP2L().keySet()) {
+                            for (String belPinName : rtCopy.getUsedPhysicalPins()) {
                                 BELPin tmp = rtCopy.getBEL().getPin(belPinName);
                                 if (tmp.isInput()) {
                                     curr = tmp;

src/com/xilinx/rapidwright/design/Unisim.java

@@ -33,12 +33,32 @@
 import com.xilinx.rapidwright.edif.EDIFLibrary;
 
 /**
- * Generated on: Wed May 01 19:57:08 MDT 2024
+ * Generated on: Thu Nov 21 13:34:09 MST 2024
  * by: com.xilinx.rapidwright.release.UnisimParser
  *
  * Enumerates supported Unisim primitives that map to Xilinx devices.
  */
 public enum Unisim {
+    AIE2PS_NOC_M_AXI,
+    AIE2PS_NOC_M_AXIS,
+    AIE2PS_NOC_S_AXI,
+    AIE2PS_NOC_S_AXIS,
+    AIE2PS_PL_M_AXIS128,
+    AIE2PS_PL_M_AXIS32,
+    AIE2PS_PL_M_AXIS64,
+    AIE2PS_PL_M_EVENTS,
+    AIE2PS_PL_S_AXIS128,
+    AIE2PS_PL_S_AXIS32,
+    AIE2PS_PL_S_AXIS64,
+    AIE2PS_PL_S_EVENTS,
+    AIE2P_PL_M_AXIS128,
+    AIE2P_PL_M_AXIS32,
+    AIE2P_PL_M_AXIS64,
+    AIE2P_PL_M_EVENTS,
+    AIE2P_PL_S_AXIS128,
+    AIE2P_PL_S_AXIS32,
+    AIE2P_PL_S_AXIS64,
+    AIE2P_PL_S_EVENTS,
     AIE_ML_NOC_M_AXI,
     AIE_ML_NOC_M_AXIS,
     AIE_ML_NOC_S_AXI,
@@ -85,6 +105,8 @@ public enum Unisim {
     AND5B4,
     AND5B5,
     AUTOBUF,
+    AXI32,
+    BFR_FT,
     BFR_MATMULX,
     BIBUF,
     BITSLICE_CONTROL,
@@ -157,8 +179,10 @@ public enum Unisim {
     DDRMC,
     DDRMC5,
     DDRMC5C,
+    DDRMC5E,
     DDRMC_RIU,
     DFE_CFR,
+    DFE_CHANNELIZER,
     DFE_DUC_DDC,
     DFE_FFT,
     DFE_FIR,
@@ -258,6 +282,7 @@ public enum Unisim {
     FRAME_ECCE3,
     FRAME_ECCE4,
     FRAME_ECC_VIRTEX6,
+    FUSE_CLK,
     GND,
     GTF_CHANNEL,
     GTF_COMMON,
@@ -769,6 +794,7 @@ public enum Unisim {
     NOC2_NMU256,
     NOC2_NMU512,
     NOC2_NPS5555,
+    NOC2_NPS6X,
     NOC2_NPS7575,
     NOC2_NSU128,
     NOC2_NSU256,
@@ -1193,6 +1219,7 @@ public enum Unisim {
     PLLE4_BASE,
     PLL_ADV,
     PLL_BASE,
+    PS11,
     PS7,
     PS8,
     PS9,
@@ -1290,9 +1317,11 @@ public enum Unisim {
     RAMS64E1,
     RAMS64E5,
     RFADC,
+    RFADCE5,
     RFADC_13B4W_M0,
     RFADC_13B4W_M1,
     RFDAC,
+    RFDACE5,
     RIU_OR,
     ROM128X1,
     ROM16X1,
@@ -1301,8 +1330,10 @@ public enum Unisim {
     ROM64X1,
     RXTX_BITSLICE,
     RX_BITSLICE,
+    SDFEC_LD,
     SIM_CONFIGE2,
     SIM_CONFIGE3,
+    SIM_CONFIGE4,
     SRL16,
     SRL16E,
     SRL16E_1,

src/com/xilinx/rapidwright/design/tools/LUTTools.java

@@ -390,9 +390,9 @@ public static EDIFPropertyValue configureLUT(EDIFCellInst c, String equation) {
      */
     public static String getLUTEquation(Cell c) {
         if (c.isRoutethru()) {
-            Set<Entry<String, String>> entrySet = c.getPinMappingsP2L().entrySet();
-            assert (entrySet.size() == 1);
-            return "O" + c.getBELName().charAt(1) + "=" + entrySet.iterator().next().getKey();
+            BELPin rtEntry = c.getFirstPhysicalPinMapping().getFirst();
+            assert (c.getUsedPhysicalPinsCount() == 1);
+            return "O" + c.getBELName().charAt(1) + "=" + rtEntry.getName();
         }
         return getLUTEquation(c.getEDIFCellInst());
     }

src/com/xilinx/rapidwright/device/FamilyType.java

@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Wed May 01 19:03:12 MDT 2024
+ * Generated on: Thu Nov 21 13:06:39 MST 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Set of all Supported Xilinx families in RapidWright
@@ -54,7 +54,9 @@ public enum FamilyType {
         QKINTEXUPLUS,
         QRKINTEXU,
         QRVERSALAICORE,
+        QRVERSALAIEDGE,
         QVERSALAICORE,
+        QVERSALAIEDGE,
         QVERSALPREMIUM,
         QVERSALPRIME,
         QVIRTEX7,

src/com/xilinx/rapidwright/device/IOBankType.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Wed May 17 23:03:43 2023
+ * Generated on: Thu Nov 21 13:34:08 MST 2024
  * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
  *
  * Enumeration of IOBankType type for all valid devices within Vivado.
@@ -41,5 +41,7 @@ public enum IOBankType {
     BT_MGT,
     BT_NO_USER_IO,
     BT_PSS,
+    BT_X5,
+    BT_X5IO,
     BT_XP,
 }

src/com/xilinx/rapidwright/device/IOStandard.java

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * Copyright (c) 2024, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Author: Chris Lavin, Advanced Micro Devices, Inc.
@@ -27,7 +27,7 @@
 
 
 /**
- * Generated on: Wed May 17 23:03:43 2023
+ * Generated on: Thu Nov 21 13:34:08 MST 2024
  * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
  *
  * Enumeration of IOStandard type for all valid devices within Vivado.
@@ -53,13 +53,18 @@ public enum IOStandard {
     DIFF_HSTL_I_DCI_18,
     DIFF_HSUL_12,
     DIFF_HSUL_12_DCI,
+    DIFF_LVSTL05_10,
+    DIFF_LVSTL05_10_HS,
     DIFF_LVSTL06_12,
     DIFF_LVSTL_11,
     DIFF_MOBILE_DDR,
     DIFF_POD10,
     DIFF_POD10_DCI,
+    DIFF_POD11,
     DIFF_POD12,
     DIFF_POD12_DCI,
+    DIFF_SSTL10,
+    DIFF_SSTL11,
     DIFF_SSTL12,
     DIFF_SSTL12_DCI,
     DIFF_SSTL12_LVAUX,
@@ -96,6 +101,8 @@ public enum IOStandard {
     HSTL_I_DCI_18,
     HSUL_12,
     HSUL_12_DCI,
+    LVCMOS10,
+    LVCMOS11,
     LVCMOS12,
     LVCMOS12_LVAUX,
     LVCMOS15,
@@ -107,27 +114,34 @@ public enum IOStandard {
     LVDCI_DV2_15,
     LVDCI_DV2_18,
     LVDS,
+    LVDS12,
     LVDS12_LVAUX,
     LVDS15,
     LVDS_25,
     LVPECL,
+    LVSTL05_10,
+    LVSTL05_10_HS,
     LVSTL06_12,
     LVSTL_11,
     LVTTL,
     MINI_LVDS_25,
+    MIPI_CPHY,
     MIPI_DPHY,
     MIPI_DPHY_DCI,
     MIPI_DPHY_LVAUX,
     MOBILE_DDR,
     PCI33_3,
     POD10,
     POD10_DCI,
+    POD11,
     POD12,
     POD12_DCI,
     PPDS_25,
     RSDS_25,
     SLVS_400_18,
     SLVS_400_25,
+    SSTL10,
+    SSTL11,
     SSTL12,
     SSTL12_DCI,
     SSTL12_LVAUX,

src/com/xilinx/rapidwright/device/Part.java

@@ -30,7 +30,7 @@
 import java.util.HashSet;
 
 /**
- * Generated on: Wed May 01 19:03:12 MDT 2024
+ * Generated on: Thu Nov 21 13:06:39 MST 2024
  * by: com.xilinx.rapidwright.release.PartNamePopulator
  *
  * Class used to uniquely represent a Xilinx part.
@@ -260,7 +260,9 @@ public Series getSeries() {
         versalTypes = new FamilyType[] {
                 FamilyType.AVERSALAIEDGE,
                 FamilyType.QRVERSALAICORE,
+                FamilyType.QRVERSALAIEDGE,
                 FamilyType.QVERSALAICORE,
+                FamilyType.QVERSALAIEDGE,
                 FamilyType.QVERSALPREMIUM,
                 FamilyType.QVERSALPRIME,
                 FamilyType.VERSAL,