RapidWright v2018.2.5-beta Release

Notes:

• Fixes an issue in
  com.xilinx.rapidwright.device.Tile.getWireConnections(int wire) that was
  causing an issue when routing clocking routes. This was manifesting
  in the SLRCrosserGenerator demo.
  Known Issues:
• Netlists that have two ports by same name where one is a single bit
  bus and another is multi-bit are not currently supported (for
  example, a module has an input 'my_signal' and 'my_signal[2:0]' is
  currently not allowed in the EDIF parser.
• Clock router in Router class is disabled (under development).
• PolynomialGenerator is a toy demonstration and does not produce a
  functionally valid circuit.

NOTE: rapidwright_data.zip has not changed since 2018.2.0 and is not required to be re-downloaded to update.