RapidWright 2018.3.0-beta Release
clavin-xlnx
released this
11 Jan 02:47
·
1796 commits
to master
since this release
Notes:
- Compatibility with Vivado 2018.3.0 and its devices
- Adds support for RapidWright Jupyter Notebook kernels
- Reduces device file size to improve download times and load times
- Removes Hessian implementation dependency for PartNameTools resource file and
ModuleCache files. This was done to resolve Java >=9 issues with
obsolete reflection usage. - Removed com.xilinx.rapidwright.edif.InstPair class and replaced functionality
with com.xilinx.rapidwright.edif.EDIFHierCellInst. - API Additions:
- com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin)"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin)"
- com.xilinx.rapidwright.design.SiteInst "public Set getSiteWiresFromNet(Net net)"
- com.xilinx.rapidwright.device.Device "public Node getNode(String name)"
- com.xilinx.rapidwright.device.Device "public Wire getWire(String name)"
- com.xilinx.rapidwright.device.Device "public PIP getPIP(String name)"
- com.xilinx.rapidwright.device.Device "public SitePin getSitePin(String name)"
- com.xilinx.rapidwright.device.Site "public Integer getSiteWireIndex(String siteWireName)"
- com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(int siteWireIndex)"
- com.xilinx.rapidwright.device.Site "public BELPin[] getBELPins(String siteWireName)"
- com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input)"
- com.xilinx.rapidwright.device.Wire "public Node getNode()"
- Deprecated APIs:
- com.xilinx.rapidwright.design.SiteInst "public void addSitePIP(String belName, String inputPin, String outputPin)"
- com.xilinx.rapidwright.design.SiteInst "public SitePIP getSitePIP(String belName, String inputPin, String outputPin)"
- com.xilinx.rapidwright.device.Site "public BELPin[] getConnectedBELPins(int siteWireIndex)"
- com.xilinx.rapidwright.device.Site "public SitePIP getSitePIP(BELPin input, BELPin output)"
Known Issues:
- Netlists that have two ports by same name where one is a single bit
bus and another is multi-bit are not currently supported (for
example, a module has an input 'my_signal' and 'my_signal[2:0]' is
currently not allowed in the EDIF parser. - Clock router in Router class is disabled (under development).
- PolynomialGenerator is a toy demonstration and does not produce a
functionally valid circuit.